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GET /api/patches/97500/?format=api
{ "id": 97500, "url": "http://patchwork.dpdk.org/api/patches/97500/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1630135806-21931-8-git-send-email-fengchengwen@huawei.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1630135806-21931-8-git-send-email-fengchengwen@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1630135806-21931-8-git-send-email-fengchengwen@huawei.com", "date": "2021-08-28T07:30:05", "name": "[v17,7/8] app/test: add dmadev API test", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "146b3877f9bac5dadddc2ac7f2fc0f4708f526dd", "submitter": { "id": 2146, "url": "http://patchwork.dpdk.org/api/people/2146/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1630135806-21931-8-git-send-email-fengchengwen@huawei.com/mbox/", "series": [ { "id": 18502, "url": "http://patchwork.dpdk.org/api/series/18502/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18502", "date": "2021-08-28T07:29:58", "name": "support dmadev", "version": 17, "mbox": "http://patchwork.dpdk.org/series/18502/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97500/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/97500/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 896D5A0C5C;\n\tSat, 28 Aug 2021 09:34:59 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B70534121F;\n\tSat, 28 Aug 2021 09:34:17 +0200 (CEST)", "from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189])\n by mails.dpdk.org (Postfix) with ESMTP id B28F64067C\n for <dev@dpdk.org>; Sat, 28 Aug 2021 09:34:07 +0200 (CEST)", "from dggemv703-chm.china.huawei.com (unknown [172.30.72.54])\n by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4GxSxm2M1Zz8Br7;\n Sat, 28 Aug 2021 15:33:48 +0800 (CST)", "from dggpeml500024.china.huawei.com (7.185.36.10) by\n dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2176.2; Sat, 28 Aug 2021 15:34:06 +0800", "from localhost.localdomain (10.67.165.24) by\n dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2176.2; Sat, 28 Aug 2021 15:34:06 +0800" ], "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<thomas@monjalon.net>, <ferruh.yigit@intel.com>,\n <bruce.richardson@intel.com>, <jerinj@marvell.com>, <jerinjacobk@gmail.com>,\n <andrew.rybchenko@oktetlabs.ru>", "CC": "<dev@dpdk.org>, <mb@smartsharesystems.com>, <nipun.gupta@nxp.com>,\n <hemant.agrawal@nxp.com>, <maxime.coquelin@redhat.com>,\n <honnappa.nagarahalli@arm.com>, <david.marchand@redhat.com>,\n <sburla@marvell.com>, <pkapoor@marvell.com>, <konstantin.ananyev@intel.com>", "Date": "Sat, 28 Aug 2021 15:30:05 +0800", "Message-ID": "<1630135806-21931-8-git-send-email-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.8.1", "In-Reply-To": "<1630135806-21931-1-git-send-email-fengchengwen@huawei.com>", "References": "<1625231891-2963-1-git-send-email-fengchengwen@huawei.com>\n <1630135806-21931-1-git-send-email-fengchengwen@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.165.24]", "X-ClientProxiedBy": "dggems703-chm.china.huawei.com (10.3.19.180) To\n dggpeml500024.china.huawei.com (7.185.36.10)", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH v17 7/8] app/test: add dmadev API test", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch add dmadev API test which based on 'dma_skeleton' vdev. The\ntest cases could be executed using 'dmadev_autotest' command in test\nframework.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n app/test/meson.build | 4 +\n app/test/test_dmadev.c | 45 ++++\n app/test/test_dmadev_api.c | 517 +++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 566 insertions(+)\n create mode 100644 app/test/test_dmadev.c\n create mode 100644 app/test/test_dmadev_api.c", "diff": "diff --git a/app/test/meson.build b/app/test/meson.build\nindex a761168..9027eba 100644\n--- a/app/test/meson.build\n+++ b/app/test/meson.build\n@@ -43,6 +43,8 @@ test_sources = files(\n 'test_debug.c',\n 'test_distributor.c',\n 'test_distributor_perf.c',\n+ 'test_dmadev.c',\n+ 'test_dmadev_api.c',\n 'test_eal_flags.c',\n 'test_eal_fs.c',\n 'test_efd.c',\n@@ -162,6 +164,7 @@ test_deps = [\n 'cmdline',\n 'cryptodev',\n 'distributor',\n+ 'dmadev',\n 'efd',\n 'ethdev',\n 'eventdev',\n@@ -333,6 +336,7 @@ driver_test_names = [\n 'cryptodev_sw_mvsam_autotest',\n 'cryptodev_sw_snow3g_autotest',\n 'cryptodev_sw_zuc_autotest',\n+ 'dmadev_autotest',\n 'eventdev_selftest_octeontx',\n 'eventdev_selftest_sw',\n 'rawdev_autotest',\ndiff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c\nnew file mode 100644\nindex 0000000..bb01e86\n--- /dev/null\n+++ b/app/test/test_dmadev.c\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 HiSilicon Limited.\n+ * Copyright(c) 2021 Intel Corporation.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_dev.h>\n+#include <rte_dmadev.h>\n+#include <rte_bus_vdev.h>\n+\n+#include \"test.h\"\n+\n+/* from test_dmadev_api.c */\n+extern int test_dmadev_api(uint16_t dev_id);\n+\n+static int\n+test_apis(void)\n+{\n+\tconst char *pmd = \"dma_skeleton\";\n+\tint id;\n+\tint ret;\n+\n+\tif (rte_vdev_init(pmd, NULL) < 0)\n+\t\treturn TEST_SKIPPED;\n+\tid = rte_dmadev_get_dev_id(pmd);\n+\tif (id < 0)\n+\t\treturn TEST_SKIPPED;\n+\tprintf(\"\\n### Test dmadev infrastructure using skeleton driver\\n\");\n+\tret = test_dmadev_api(id);\n+\trte_vdev_uninit(pmd);\n+\n+\treturn ret;\n+}\n+\n+static int\n+test_dmadev(void)\n+{\n+\t/* basic sanity on dmadev infrastructure */\n+\tif (test_apis() < 0)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+REGISTER_TEST_COMMAND(dmadev_autotest, test_dmadev);\ndiff --git a/app/test/test_dmadev_api.c b/app/test/test_dmadev_api.c\nnew file mode 100644\nindex 0000000..aefd4aa\n--- /dev/null\n+++ b/app/test/test_dmadev_api.c\n@@ -0,0 +1,517 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 HiSilicon Limited.\n+ */\n+\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_malloc.h>\n+#include <rte_test.h>\n+#include <rte_dmadev.h>\n+\n+extern int test_dmadev_api(uint16_t dev_id);\n+\n+#define SKELDMA_TEST_RUN(test) \\\n+\ttestsuite_run_test(test, #test)\n+\n+#define TEST_MEMCPY_SIZE\t1024\n+#define TEST_WAIT_US_VAL\t50000\n+\n+#define TEST_SUCCESS 0\n+#define TEST_FAILED -1\n+\n+static uint16_t test_dev_id;\n+static uint16_t invalid_dev_id;\n+\n+static int total;\n+static int passed;\n+static int failed;\n+static char *src;\n+static char *dst;\n+\n+static int\n+testsuite_setup(uint16_t dev_id)\n+{\n+\ttest_dev_id = dev_id;\n+\tinvalid_dev_id = RTE_DMADEV_MAX_DEVS;\n+\n+\tsrc = rte_malloc(\"dmadev_test_src\", TEST_MEMCPY_SIZE, 0);\n+\tif (src == NULL)\n+\t\treturn -ENOMEM;\n+\tdst = rte_malloc(\"dmadev_test_dst\", TEST_MEMCPY_SIZE, 0);\n+\tif (dst == NULL)\n+\t\treturn -ENOMEM;\n+\n+\ttotal = 0;\n+\tpassed = 0;\n+\tfailed = 0;\n+\n+\treturn 0;\n+}\n+\n+static void\n+testsuite_teardown(void)\n+{\n+\trte_free(src);\n+\trte_free(dst);\n+\t/* Ensure the dmadev is stopped. */\n+\trte_dmadev_stop(test_dev_id);\n+}\n+\n+static void\n+testsuite_run_test(int (*test)(void), const char *name)\n+{\n+\tint ret = 0;\n+\n+\tif (test) {\n+\t\tret = test();\n+\t\tif (ret < 0) {\n+\t\t\tfailed++;\n+\t\t\tprintf(\"%s Failed\\n\", name);\n+\t\t} else {\n+\t\t\tpassed++;\n+\t\t\tprintf(\"%s Passed\\n\", name);\n+\t\t}\n+\t}\n+\n+\ttotal++;\n+}\n+\n+static int\n+test_dmadev_get_dev_id(void)\n+{\n+\tint ret = rte_dmadev_get_dev_id(\"invalid_dmadev_device\");\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_is_valid_dev(void)\n+{\n+\tint ret;\n+\tret = rte_dmadev_is_valid_dev(invalid_dev_id);\n+\tRTE_TEST_ASSERT(ret == false, \"Expected false for invalid dev id\");\n+\tret = rte_dmadev_is_valid_dev(test_dev_id);\n+\tRTE_TEST_ASSERT(ret == true, \"Expected true for valid dev id\");\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_count(void)\n+{\n+\tuint16_t count = rte_dmadev_count();\n+\tRTE_TEST_ASSERT(count > 0, \"Invalid dmadev count %u\", count);\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_info_get(void)\n+{\n+\tstruct rte_dmadev_info info = { 0 };\n+\tint ret;\n+\n+\tret = rte_dmadev_info_get(invalid_dev_id, &info);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_info_get(test_dev_id, NULL);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_info_get(test_dev_id, &info);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to obtain device info\");\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_configure(void)\n+{\n+\tstruct rte_dmadev_conf conf = { 0 };\n+\tstruct rte_dmadev_info info = { 0 };\n+\tint ret;\n+\n+\t/* Check for invalid parameters */\n+\tret = rte_dmadev_configure(invalid_dev_id, &conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_configure(test_dev_id, NULL);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check for nb_vchans == 0 */\n+\tmemset(&conf, 0, sizeof(conf));\n+\tret = rte_dmadev_configure(test_dev_id, &conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check for conf.nb_vchans > info.max_vchans */\n+\tret = rte_dmadev_info_get(test_dev_id, &info);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to obtain device info\");\n+\tmemset(&conf, 0, sizeof(conf));\n+\tconf.nb_vchans = info.max_vchans + 1;\n+\tret = rte_dmadev_configure(test_dev_id, &conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check enable silent mode */\n+\tmemset(&conf, 0, sizeof(conf));\n+\tconf.nb_vchans = info.max_vchans;\n+\tconf.enable_silent = true;\n+\tret = rte_dmadev_configure(test_dev_id, &conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Configure success */\n+\tmemset(&conf, 0, sizeof(conf));\n+\tconf.nb_vchans = info.max_vchans;\n+\tret = rte_dmadev_configure(test_dev_id, &conf);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to configure dmadev, %d\", ret);\n+\n+\t/* Check configure success */\n+\tret = rte_dmadev_info_get(test_dev_id, &info);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to obtain device info\");\n+\tRTE_TEST_ASSERT_EQUAL(conf.nb_vchans, info.nb_vchans,\n+\t\t\t \"Configure nb_vchans not match\");\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_vchan_setup(void)\n+{\n+\tstruct rte_dmadev_vchan_conf vchan_conf = { 0 };\n+\tstruct rte_dmadev_conf dev_conf = { 0 };\n+\tstruct rte_dmadev_info dev_info = { 0 };\n+\tint ret;\n+\n+\t/* Check for invalid parameters */\n+\tret = rte_dmadev_vchan_setup(invalid_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, NULL);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Make sure configure success */\n+\tret = rte_dmadev_info_get(test_dev_id, &dev_info);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to obtain device info\");\n+\tdev_conf.nb_vchans = dev_info.max_vchans;\n+\tret = rte_dmadev_configure(test_dev_id, &dev_conf);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to configure dmadev, %d\", ret);\n+\n+\t/* Check for invalid vchan */\n+\tret = rte_dmadev_vchan_setup(test_dev_id, dev_conf.nb_vchans,\n+\t\t\t\t &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check for direction */\n+\tmemset(&vchan_conf, 0, sizeof(vchan_conf));\n+\tvchan_conf.direction = RTE_DMA_DIR_DEV_TO_DEV + 1;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tvchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM - 1;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check for direction and dev_capa combination */\n+\tmemset(&vchan_conf, 0, sizeof(vchan_conf));\n+\tvchan_conf.direction = RTE_DMA_DIR_MEM_TO_DEV;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tvchan_conf.direction = RTE_DMA_DIR_DEV_TO_MEM;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tvchan_conf.direction = RTE_DMA_DIR_DEV_TO_DEV;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check for nb_desc validation */\n+\tmemset(&vchan_conf, 0, sizeof(vchan_conf));\n+\tvchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;\n+\tvchan_conf.nb_desc = dev_info.min_desc - 1;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tvchan_conf.nb_desc = dev_info.max_desc + 1;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check src port type validation */\n+\tmemset(&vchan_conf, 0, sizeof(vchan_conf));\n+\tvchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;\n+\tvchan_conf.nb_desc = dev_info.min_desc;\n+\tvchan_conf.src_port.port_type = RTE_DMADEV_PORT_PCIE;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check dst port type validation */\n+\tmemset(&vchan_conf, 0, sizeof(vchan_conf));\n+\tvchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;\n+\tvchan_conf.nb_desc = dev_info.min_desc;\n+\tvchan_conf.dst_port.port_type = RTE_DMADEV_PORT_PCIE;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check vchan setup success */\n+\tmemset(&vchan_conf, 0, sizeof(vchan_conf));\n+\tvchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;\n+\tvchan_conf.nb_desc = dev_info.min_desc;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup vchan, %d\", ret);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+setup_one_vchan(void)\n+{\n+\tstruct rte_dmadev_vchan_conf vchan_conf = { 0 };\n+\tstruct rte_dmadev_info dev_info = { 0 };\n+\tstruct rte_dmadev_conf dev_conf = { 0 };\n+\tint ret;\n+\n+\tret = rte_dmadev_info_get(test_dev_id, &dev_info);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to obtain device info, %d\", ret);\n+\tdev_conf.nb_vchans = dev_info.max_vchans;\n+\tret = rte_dmadev_configure(test_dev_id, &dev_conf);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to configure, %d\", ret);\n+\tvchan_conf.direction = RTE_DMA_DIR_MEM_TO_MEM;\n+\tvchan_conf.nb_desc = dev_info.min_desc;\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup vchan, %d\", ret);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_start_stop(void)\n+{\n+\tstruct rte_dmadev_vchan_conf vchan_conf = { 0 };\n+\tstruct rte_dmadev_conf dev_conf = { 0 };\n+\tint ret;\n+\n+\t/* Check for invalid parameters */\n+\tret = rte_dmadev_start(invalid_dev_id);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_stop(invalid_dev_id);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Setup one vchan for later test */\n+\tret = setup_one_vchan();\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup one vchan, %d\", ret);\n+\n+\tret = rte_dmadev_start(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to start, %d\", ret);\n+\n+\t/* Check reconfigure and vchan setup when device started */\n+\tret = rte_dmadev_configure(test_dev_id, &dev_conf);\n+\tRTE_TEST_ASSERT(ret == -EBUSY, \"Failed to configure, %d\", ret);\n+\tret = rte_dmadev_vchan_setup(test_dev_id, 0, &vchan_conf);\n+\tRTE_TEST_ASSERT(ret == -EBUSY, \"Failed to setup vchan, %d\", ret);\n+\n+\tret = rte_dmadev_stop(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to stop, %d\", ret);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_stats(void)\n+{\n+\tstruct rte_dmadev_info dev_info = { 0 };\n+\tstruct rte_dmadev_stats stats = { 0 };\n+\tint ret;\n+\n+\t/* Check for invalid parameters */\n+\tret = rte_dmadev_stats_get(invalid_dev_id, 0, &stats);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_stats_get(invalid_dev_id, 0, NULL);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_stats_reset(invalid_dev_id, 0);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Setup one vchan for later test */\n+\tret = setup_one_vchan();\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup one vchan, %d\", ret);\n+\n+\t/* Check for invalid vchan */\n+\tret = rte_dmadev_info_get(test_dev_id, &dev_info);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to obtain device info, %d\", ret);\n+\tret = rte_dmadev_stats_get(test_dev_id, dev_info.max_vchans, &stats);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\tret = rte_dmadev_stats_reset(test_dev_id, dev_info.max_vchans);\n+\tRTE_TEST_ASSERT(ret == -EINVAL, \"Expected -EINVAL, %d\", ret);\n+\n+\t/* Check for valid vchan */\n+\tret = rte_dmadev_stats_get(test_dev_id, 0, &stats);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to get stats, %d\", ret);\n+\tret = rte_dmadev_stats_get(test_dev_id, RTE_DMADEV_ALL_VCHAN, &stats);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to get all stats, %d\", ret);\n+\tret = rte_dmadev_stats_reset(test_dev_id, 0);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to reset stats, %d\", ret);\n+\tret = rte_dmadev_stats_reset(test_dev_id, RTE_DMADEV_ALL_VCHAN);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to reset all stats, %d\", ret);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_completed(void)\n+{\n+\tuint16_t last_idx = 1;\n+\tbool has_error = true;\n+\tuint16_t cpl_ret;\n+\tint ret, i;\n+\n+\t/* Setup one vchan for later test */\n+\tret = setup_one_vchan();\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup one vchan, %d\", ret);\n+\n+\tret = rte_dmadev_start(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to start, %d\", ret);\n+\n+\t/* Setup test memory */\n+\tfor (i = 0; i < TEST_MEMCPY_SIZE; i++)\n+\t\tsrc[i] = (char)i;\n+\tmemset(dst, 0, TEST_MEMCPY_SIZE);\n+\n+\t/* Check enqueue without submit */\n+\tret = rte_dmadev_copy(test_dev_id, 0, (rte_iova_t)src, (rte_iova_t)dst,\n+\t\t\t\tTEST_MEMCPY_SIZE, 0);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to enqueue copy, %d\", ret);\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\tcpl_ret = rte_dmadev_completed(test_dev_id, 0, 1, &last_idx,\n+\t\t\t\t &has_error);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 0, \"Failed to get completed\");\n+\n+\t/* Check add submit */\n+\tret = rte_dmadev_submit(test_dev_id, 0);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to submit, %d\", ret);\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\tcpl_ret = rte_dmadev_completed(test_dev_id, 0, 1, &last_idx,\n+\t\t\t\t &has_error);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 1, \"Failed to get completed\");\n+\tRTE_TEST_ASSERT_EQUAL(last_idx, 0, \"Last idx should be zero, %u\",\n+\t\t\t\tlast_idx);\n+\tRTE_TEST_ASSERT_EQUAL(has_error, false, \"Should have no error\");\n+\tfor (i = 0; i < TEST_MEMCPY_SIZE; i++) {\n+\t\tif (src[i] != dst[i]) {\n+\t\t\tRTE_TEST_ASSERT_EQUAL(src[i], dst[i],\n+\t\t\t\t\"Failed to copy memory, %d %d\", src[i], dst[i]);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Setup test memory */\n+\tfor (i = 0; i < TEST_MEMCPY_SIZE; i++)\n+\t\tsrc[i] = (char)i;\n+\tmemset(dst, 0, TEST_MEMCPY_SIZE);\n+\n+\t/* Check for enqueue with submit */\n+\tret = rte_dmadev_copy(test_dev_id, 0, (rte_iova_t)src, (rte_iova_t)dst,\n+\t\t\t\tTEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to enqueue copy, %d\", ret);\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\tcpl_ret = rte_dmadev_completed(test_dev_id, 0, 1, &last_idx,\n+\t\t\t\t &has_error);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 1, \"Failed to get completed\");\n+\tRTE_TEST_ASSERT_EQUAL(last_idx, 1, \"Last idx should be 1, %u\",\n+\t\t\t\tlast_idx);\n+\tRTE_TEST_ASSERT_EQUAL(has_error, false, \"Should have no error\");\n+\tfor (i = 0; i < TEST_MEMCPY_SIZE; i++) {\n+\t\tif (src[i] != dst[i]) {\n+\t\t\tRTE_TEST_ASSERT_EQUAL(src[i], dst[i],\n+\t\t\t\t\"Failed to copy memory, %d %d\", src[i], dst[i]);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Stop dmadev to make sure dmadev to a known state */\n+\tret = rte_dmadev_stop(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to stop, %d\", ret);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_dmadev_completed_status(void)\n+{\n+\tenum rte_dma_status_code status[1] = { 1 };\n+\tuint16_t last_idx = 1;\n+\tuint16_t cpl_ret, i;\n+\tint ret;\n+\n+\t/* Setup one vchan for later test */\n+\tret = setup_one_vchan();\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup one vchan, %d\", ret);\n+\n+\tret = rte_dmadev_start(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to start, %d\", ret);\n+\n+\t/* Check for enqueue with submit */\n+\tret = rte_dmadev_copy(test_dev_id, 0, (rte_iova_t)src, (rte_iova_t)dst,\n+\t\t\t\tTEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to enqueue copy, %d\", ret);\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\tcpl_ret = rte_dmadev_completed_status(test_dev_id, 0, 1, &last_idx,\n+\t\t\t\t\t status);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 1, \"Failed to completed status\");\n+\tRTE_TEST_ASSERT_EQUAL(last_idx, 0, \"Last idx should be zero, %u\",\n+\t\t\t\tlast_idx);\n+\tfor (i = 0; i < RTE_DIM(status); i++)\n+\t\tRTE_TEST_ASSERT_EQUAL(status[i], 0,\n+\t\t\t\t\"Failed to completed status, %d\", status[i]);\n+\n+\t/* Check do completed status again */\n+\tcpl_ret = rte_dmadev_completed_status(test_dev_id, 0, 1, &last_idx,\n+\t\t\t\t\t status);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 0, \"Failed to completed status\");\n+\n+\t/* Check for enqueue with submit again */\n+\tret = rte_dmadev_copy(test_dev_id, 0, (rte_iova_t)src, (rte_iova_t)dst,\n+\t\t\t\tTEST_MEMCPY_SIZE, RTE_DMA_OP_FLAG_SUBMIT);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to enqueue copy, %d\", ret);\n+\trte_delay_us_sleep(TEST_WAIT_US_VAL);\n+\tcpl_ret = rte_dmadev_completed_status(test_dev_id, 0, 1, &last_idx,\n+\t\t\t\t\t status);\n+\tRTE_TEST_ASSERT_EQUAL(cpl_ret, 1, \"Failed to completed status\");\n+\tRTE_TEST_ASSERT_EQUAL(last_idx, 1, \"Last idx should be 1, %u\",\n+\t\t\t\tlast_idx);\n+\tfor (i = 0; i < RTE_DIM(status); i++)\n+\t\tRTE_TEST_ASSERT_EQUAL(status[i], 0,\n+\t\t\t\t\"Failed to completed status, %d\", status[i]);\n+\n+\t/* Stop dmadev to make sure dmadev to a known state */\n+\tret = rte_dmadev_stop(test_dev_id);\n+\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to stop, %d\", ret);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+int\n+test_dmadev_api(uint16_t dev_id)\n+{\n+\tint ret = testsuite_setup(dev_id);\n+\tif (ret) {\n+\t\tprintf(\"testsuite setup fail!\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* If the testcase exit successfully, ensure that the test dmadev exist\n+\t * and the dmadev is in the stopped state.\n+\t */\n+\tSKELDMA_TEST_RUN(test_dmadev_get_dev_id);\n+\tSKELDMA_TEST_RUN(test_dmadev_is_valid_dev);\n+\tSKELDMA_TEST_RUN(test_dmadev_count);\n+\tSKELDMA_TEST_RUN(test_dmadev_info_get);\n+\tSKELDMA_TEST_RUN(test_dmadev_configure);\n+\tSKELDMA_TEST_RUN(test_dmadev_vchan_setup);\n+\tSKELDMA_TEST_RUN(test_dmadev_start_stop);\n+\tSKELDMA_TEST_RUN(test_dmadev_stats);\n+\tSKELDMA_TEST_RUN(test_dmadev_completed);\n+\tSKELDMA_TEST_RUN(test_dmadev_completed_status);\n+\n+\ttestsuite_teardown();\n+\n+\tprintf(\"Total tests : %d\\n\", total);\n+\tprintf(\"Passed : %d\\n\", passed);\n+\tprintf(\"Failed : %d\\n\", failed);\n+\n+\tif (failed)\n+\t\treturn -1;\n+\n+\treturn 0;\n+};\n", "prefixes": [ "v17", "7/8" ] }