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GET /api/patches/99690/?format=api
{ "id": 99690, "url": "http://patchwork.dpdk.org/api/patches/99690/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210926111904.237736-7-xuemingl@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210926111904.237736-7-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210926111904.237736-7-xuemingl@nvidia.com", "date": "2021-09-26T11:18:59", "name": "[06/11] net/mlx5: move Rx queue reference count", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d51fc7f6512398dc44670d27ee2f0cd5c931e76b", "submitter": { "id": 1904, "url": "http://patchwork.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210926111904.237736-7-xuemingl@nvidia.com/mbox/", "series": [ { "id": 19166, "url": "http://patchwork.dpdk.org/api/series/19166/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=19166", "date": "2021-09-26T11:18:53", "name": "net/mlx5: support shared Rx queue", "version": 1, "mbox": "http://patchwork.dpdk.org/series/19166/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/99690/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/99690/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8F019A0548;\n\tSun, 26 Sep 2021 13:20:15 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0D427410FF;\n\tSun, 26 Sep 2021 13:20:11 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2059.outbound.protection.outlook.com [40.107.237.59])\n by mails.dpdk.org (Postfix) with ESMTP id BDB2F410F7\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<xuemingl@nvidia.com>, Lior Margalit <lmargalit@nvidia.com>, Matan Azrad\n <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Sun, 26 Sep 2021 19:18:59 +0800", "Message-ID": "<20210926111904.237736-7-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20210926111904.237736-1-xuemingl@nvidia.com>", "References": "<20210926111904.237736-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "3420b393-4dca-4a5f-b673-08d980df98ad", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1223:", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB1223C36B91BB6C312207370FA1A69@CY4PR12MB1223.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:513;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +Q0sY7cEiJ+7fWHN6mgDOECyA8izHJwpthQiA58vMyUN25jV8oHlE6RLGh1d2n8AOrlSG557Ap4tYDAGpkq9wYx4cc9H746ctT836D1JdHnTCwrAehahd4EVKOrOJJGA77Lrq3xpTRrU9sAbIh6GX6TZRWpKbAnZ6VWVnmQveQ2XWBre73+Z0+qNaOnLrXoPUZFFwjM+Yulfpyh16ZInbOlaZd8pi90sdH0MAuf73I2NqwP7a7BXZR7nseX+lmUmXfblWXxKWwoLptf45CYwif5+4zzbaunxML1+E/IWnvk+BYSQzSOrs+HqpQ3YRC9FlkbKWuNaQsk0ZL70jkGdodKlSaAFthm/mYYsfaCCfnFNoLOyxICnTyNB7VYzZ5xheq4bh2Zm/bsjkVwhW7w5UNI8I3iq2jssZb+jUt+WHuodVF6jajS6/ZasR/3lBGJBEr0eW5spKwjyQiXbTObrCOd48jxrC1dAl6/1PJ27PQbYwvM2+wxhdW0kBHvbYH+6VPnfLBrLIl6DaVD3LiV5rcRK6/pX74xpsZUDP3isvIt+n1KFOpQ7gB6hBpj0oYbVoiLo5fLcboJmQuiRJp3lwusUUiIbmSaOxm05Yv8wIxgYi9hePw0t+l7kXIg+w/ptNCnOfkD0Cw0m+yXzyF6EgyDsWKmT0Pn4/eJDJjrWGbOAX2QtBYVNhiu4i8Q585HgQPVwvW2HZ7IXZpVOYkpL9A==", "X-Forefront-Antispam-Report": "CIP:216.228.112.35; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid02.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(2616005)(426003)(86362001)(508600001)(356005)(336012)(7636003)(1076003)(107886003)(8676002)(6286002)(8936002)(55016002)(47076005)(186003)(70586007)(36860700001)(36756003)(7696005)(5660300002)(16526019)(83380400001)(30864003)(70206006)(6916009)(2906002)(82310400003)(26005)(54906003)(316002)(4326008)(36906005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Sep 2021 11:20:07.4401 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3420b393-4dca-4a5f-b673-08d980df98ad", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT022.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1223", "Subject": "[dpdk-dev] [PATCH 06/11] net/mlx5: move Rx queue reference count", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rx queue reference count is counter of RQ, used on RQ table.\nTo prepare for shared Rx queue, move it from rxq_ctrl to Rx queue\nprivate data.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rx.h | 8 +-\n drivers/net/mlx5/mlx5_rxq.c | 173 +++++++++++++++++++++-----------\n drivers/net/mlx5/mlx5_trigger.c | 57 +++++------\n 3 files changed, 144 insertions(+), 94 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex db6252e8e86..fe19414c130 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -160,7 +160,6 @@ enum mlx5_rxq_type {\n struct mlx5_rxq_ctrl {\n \tstruct mlx5_rxq_data rxq; /* Data path structure. */\n \tLIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */\n-\tuint32_t refcnt; /* Reference counter. */\n \tLIST_HEAD(priv, mlx5_rxq_priv) owners; /* Owner rxq list. */\n \tstruct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */\n \tstruct mlx5_dev_ctx_shared *sh; /* Shared context. */\n@@ -179,6 +178,7 @@ struct mlx5_rxq_ctrl {\n /* RX queue private data. */\n struct mlx5_rxq_priv {\n \tuint16_t idx; /* Queue index. */\n+\tuint32_t refcnt; /* Reference counter. */\n \tstruct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */\n \tLIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */\n \tstruct mlx5_priv *priv; /* Back pointer to private data. */\n@@ -216,7 +216,11 @@ struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev,\n struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new\n \t(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, uint16_t desc,\n \t const struct rte_eth_hairpin_conf *hairpin_conf);\n-struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);\n+struct mlx5_rxq_priv *mlx5_rxq_ref(struct rte_eth_dev *dev, uint16_t idx);\n+uint32_t mlx5_rxq_deref(struct rte_eth_dev *dev, uint16_t idx);\n+struct mlx5_rxq_priv *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);\n+struct mlx5_rxq_ctrl *mlx5_rxq_ctrl_get(struct rte_eth_dev *dev, uint16_t idx);\n+struct mlx5_rxq_data *mlx5_rxq_data_get(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_rxq_verify(struct rte_eth_dev *dev);\n int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 70e73690aa7..7f28646f55c 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -386,15 +386,13 @@ mlx5_get_rx_port_offloads(void)\n static int\n mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);\n \n-\tif (!(*priv->rxqs)[idx]) {\n+\tif (rxq == NULL) {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\n-\trxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);\n-\treturn (__atomic_load_n(&rxq_ctrl->refcnt, __ATOMIC_RELAXED) == 1);\n+\treturn (__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED) == 1);\n }\n \n /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */\n@@ -874,8 +872,8 @@ mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)\n \tintr_handle->type = RTE_INTR_HANDLE_EXT;\n \tfor (i = 0; i != n; ++i) {\n \t\t/* This rxq obj must not be released in this function. */\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);\n-\t\tstruct mlx5_rxq_obj *rxq_obj = rxq_ctrl ? rxq_ctrl->obj : NULL;\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i);\n+\t\tstruct mlx5_rxq_obj *rxq_obj = rxq ? rxq->ctrl->obj : NULL;\n \t\tint rc;\n \n \t\t/* Skip queues that cannot request interrupts. */\n@@ -885,11 +883,9 @@ mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)\n \t\t\tintr_handle->intr_vec[i] =\n \t\t\t\tRTE_INTR_VEC_RXTX_OFFSET +\n \t\t\t\tRTE_MAX_RXTX_INTR_VEC_ID;\n-\t\t\t/* Decrease the rxq_ctrl's refcnt */\n-\t\t\tif (rxq_ctrl)\n-\t\t\t\tmlx5_rxq_release(dev, i);\n \t\t\tcontinue;\n \t\t}\n+\t\tmlx5_rxq_ref(dev, i);\n \t\tif (count >= RTE_MAX_RXTX_INTR_VEC_ID) {\n \t\t\tDRV_LOG(ERR,\n \t\t\t\t\"port %u too many Rx queues for interrupt\"\n@@ -949,7 +945,7 @@ mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)\n \t\t * Need to access directly the queue to release the reference\n \t\t * kept in mlx5_rx_intr_vec_enable().\n \t\t */\n-\t\tmlx5_rxq_release(dev, i);\n+\t\tmlx5_rxq_deref(dev, i);\n \t}\n free:\n \trte_intr_free_epoll_fd(intr_handle);\n@@ -998,19 +994,14 @@ mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)\n int\n mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n-\n-\trxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);\n-\tif (!rxq_ctrl)\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id);\n+\tif (!rxq)\n \t\tgoto error;\n-\tif (rxq_ctrl->irq) {\n-\t\tif (!rxq_ctrl->obj) {\n-\t\t\tmlx5_rxq_release(dev, rx_queue_id);\n+\tif (rxq->ctrl->irq) {\n+\t\tif (!rxq->ctrl->obj)\n \t\t\tgoto error;\n-\t\t}\n-\t\tmlx5_arm_cq(&rxq_ctrl->rxq, rxq_ctrl->rxq.cq_arm_sn);\n+\t\tmlx5_arm_cq(&rxq->ctrl->rxq, rxq->ctrl->rxq.cq_arm_sn);\n \t}\n-\tmlx5_rxq_release(dev, rx_queue_id);\n \treturn 0;\n error:\n \trte_errno = EINVAL;\n@@ -1032,23 +1023,21 @@ int\n mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id);\n \tint ret = 0;\n \n-\trxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);\n-\tif (!rxq_ctrl) {\n+\tif (!rxq) {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\n-\tif (!rxq_ctrl->obj)\n+\tif (!rxq->ctrl->obj)\n \t\tgoto error;\n-\tif (rxq_ctrl->irq) {\n-\t\tret = priv->obj_ops.rxq_event_get(rxq_ctrl->obj);\n+\tif (rxq->ctrl->irq) {\n+\t\tret = priv->obj_ops.rxq_event_get(rxq->ctrl->obj);\n \t\tif (ret < 0)\n \t\t\tgoto error;\n-\t\trxq_ctrl->rxq.cq_arm_sn++;\n+\t\trxq->ctrl->rxq.cq_arm_sn++;\n \t}\n-\tmlx5_rxq_release(dev, rx_queue_id);\n \treturn 0;\n error:\n \t/**\n@@ -1059,12 +1048,9 @@ mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t\trte_errno = errno;\n \telse\n \t\trte_errno = EINVAL;\n-\tret = rte_errno; /* Save rte_errno before cleanup. */\n-\tmlx5_rxq_release(dev, rx_queue_id);\n-\tif (ret != EAGAIN)\n+\tif (rte_errno != EAGAIN)\n \t\tDRV_LOG(WARNING, \"port %u unable to disable interrupt on Rx queue %d\",\n \t\t\tdev->data->port_id, rx_queue_id);\n-\trte_errno = ret; /* Restore rte_errno. */\n \treturn -rte_errno;\n }\n \n@@ -1611,7 +1597,7 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \ttmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;\n #endif\n \ttmpl->rxq.idx = idx;\n-\t__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n+\tmlx5_rxq_ref(dev, idx);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\n \treturn tmpl;\n error:\n@@ -1665,11 +1651,53 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \ttmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };\n \ttmpl->hairpin_conf = *hairpin_conf;\n \ttmpl->rxq.idx = idx;\n-\t__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);\n+\tmlx5_rxq_ref(dev, idx);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\n \treturn tmpl;\n }\n \n+/**\n+ * Increase Rx queue reference count.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param idx\n+ * RX queue index.\n+ *\n+ * @return\n+ * A pointer to the queue if it exists, NULL otherwise.\n+ */\n+inline struct mlx5_rxq_priv *\n+mlx5_rxq_ref(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);\n+\n+\tif (rxq != NULL)\n+\t\t__atomic_fetch_add(&rxq->refcnt, 1, __ATOMIC_RELAXED);\n+\treturn rxq;\n+}\n+\n+/**\n+ * Dereference a Rx queue.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param idx\n+ * RX queue index.\n+ *\n+ * @return\n+ * Updated reference count.\n+ */\n+inline uint32_t\n+mlx5_rxq_deref(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);\n+\n+\tif (rxq == NULL)\n+\t\treturn 0;\n+\treturn __atomic_sub_fetch(&rxq->refcnt, 1, __ATOMIC_RELAXED);\n+}\n+\n /**\n * Get a Rx queue.\n *\n@@ -1681,18 +1709,52 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n * @return\n * A pointer to the queue if it exists, NULL otherwise.\n */\n-struct mlx5_rxq_ctrl *\n+inline struct mlx5_rxq_priv *\n mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl = NULL;\n \n-\tif (rxq_data) {\n-\t\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\t\t__atomic_fetch_add(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED);\n-\t}\n-\treturn rxq_ctrl;\n+\tif (priv->rxq_privs == NULL)\n+\t\treturn NULL;\n+\treturn (*priv->rxq_privs)[idx];\n+}\n+\n+/**\n+ * Get Rx queue shareable control.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param idx\n+ * RX queue index.\n+ *\n+ * @return\n+ * A pointer to the queue control if it exists, NULL otherwise.\n+ */\n+inline struct mlx5_rxq_ctrl *\n+mlx5_rxq_ctrl_get(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);\n+\n+\treturn rxq == NULL ? NULL : rxq->ctrl;\n+}\n+\n+/**\n+ * Get Rx queue shareable data.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param idx\n+ * RX queue index.\n+ *\n+ * @return\n+ * A pointer to the queue data if it exists, NULL otherwise.\n+ */\n+inline struct mlx5_rxq_data *\n+mlx5_rxq_data_get(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);\n+\n+\treturn rxq == NULL ? NULL : &rxq->ctrl->rxq;\n }\n \n /**\n@@ -1710,13 +1772,12 @@ int\n mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n-\tstruct mlx5_rxq_priv *rxq = (*priv->rxq_privs)[idx];\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;\n \n \tif (priv->rxqs == NULL || (*priv->rxqs)[idx] == NULL)\n \t\treturn 0;\n-\trxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);\n-\tif (__atomic_sub_fetch(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED) > 1)\n+\tif (mlx5_rxq_deref(dev, idx) > 1)\n \t\treturn 1;\n \tif (rxq_ctrl->obj) {\n \t\tpriv->obj_ops.rxq_obj_release(rxq_ctrl->obj);\n@@ -1728,7 +1789,7 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)\n \t\trxq_free_elts(rxq_ctrl);\n \t\tdev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;\n \t}\n-\tif (!__atomic_load_n(&rxq_ctrl->refcnt, __ATOMIC_RELAXED)) {\n+\tif (!__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED)) {\n \t\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {\n \t\t\tmlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);\n \t\t\tmlx5_mprq_free_mp(dev, rxq_ctrl);\n@@ -1908,7 +1969,7 @@ mlx5_ind_table_obj_release(struct rte_eth_dev *dev,\n \t\treturn 1;\n \tpriv->obj_ops.ind_table_destroy(ind_tbl);\n \tfor (i = 0; i != ind_tbl->queues_n; ++i)\n-\t\tclaim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));\n+\t\tclaim_nonzero(mlx5_rxq_deref(dev, ind_tbl->queues[i]));\n \tmlx5_free(ind_tbl);\n \treturn 0;\n }\n@@ -1965,7 +2026,7 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,\n \t\t\t log2above(priv->config.ind_table_max_size);\n \n \tfor (i = 0; i != queues_n; ++i) {\n-\t\tif (!mlx5_rxq_get(dev, queues[i])) {\n+\t\tif (mlx5_rxq_ref(dev, queues[i]) == NULL) {\n \t\t\tret = -rte_errno;\n \t\t\tgoto error;\n \t\t}\n@@ -1978,7 +2039,7 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,\n error:\n \terr = rte_errno;\n \tfor (j = 0; j < i; j++)\n-\t\tmlx5_rxq_release(dev, ind_tbl->queues[j]);\n+\t\tmlx5_rxq_deref(dev, ind_tbl->queues[j]);\n \trte_errno = err;\n \tDRV_LOG(DEBUG, \"Port %u cannot setup indirection table.\",\n \t\tdev->data->port_id);\n@@ -2074,7 +2135,7 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,\n \t\t\t bool standalone)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tunsigned int i, j;\n+\tunsigned int i;\n \tint ret = 0, err;\n \tconst unsigned int n = rte_is_power_of_2(queues_n) ?\n \t\t\t log2above(queues_n) :\n@@ -2094,15 +2155,11 @@ mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,\n \tret = priv->obj_ops.ind_table_modify(dev, n, queues, queues_n, ind_tbl);\n \tif (ret)\n \t\tgoto error;\n-\tfor (j = 0; j < ind_tbl->queues_n; j++)\n-\t\tmlx5_rxq_release(dev, ind_tbl->queues[j]);\n \tind_tbl->queues_n = queues_n;\n \tind_tbl->queues = queues;\n \treturn 0;\n error:\n \terr = rte_errno;\n-\tfor (j = 0; j < i; j++)\n-\t\tmlx5_rxq_release(dev, queues[j]);\n \trte_errno = err;\n \tDRV_LOG(DEBUG, \"Port %u cannot setup indirection table.\",\n \t\tdev->data->port_id);\n@@ -2135,7 +2192,7 @@ mlx5_ind_table_obj_attach(struct rte_eth_dev *dev,\n \t\treturn ret;\n \t}\n \tfor (i = 0; i < ind_tbl->queues_n; i++)\n-\t\tmlx5_rxq_get(dev, ind_tbl->queues[i]);\n+\t\tmlx5_rxq_ref(dev, ind_tbl->queues[i]);\n \treturn 0;\n }\n \n@@ -2172,7 +2229,7 @@ mlx5_ind_table_obj_detach(struct rte_eth_dev *dev,\n \t\treturn ret;\n \t}\n \tfor (i = 0; i < ind_tbl->queues_n; i++)\n-\t\tmlx5_rxq_release(dev, ind_tbl->queues[i]);\n+\t\tmlx5_rxq_deref(dev, ind_tbl->queues[i]);\n \treturn ret;\n }\n \ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 0753dbad053..a49254c96f6 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -143,10 +143,12 @@ mlx5_rxq_start(struct rte_eth_dev *dev)\n \tDRV_LOG(DEBUG, \"Port %u device_attr.max_sge is %d.\",\n \t\tdev->data->port_id, priv->sh->device_attr.max_sge);\n \tfor (i = 0; i != priv->rxqs_n; ++i) {\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_ref(dev, i);\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \n-\t\tif (!rxq_ctrl)\n+\t\tif (rxq == NULL)\n \t\t\tcontinue;\n+\t\trxq_ctrl = rxq->ctrl;\n \t\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {\n \t\t\tif (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq)) {\n \t\t\t\t/* Allocate/reuse/resize mempool for MPRQ. */\n@@ -215,6 +217,7 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)\n \tstruct mlx5_devx_modify_sq_attr sq_attr = { 0 };\n \tstruct mlx5_devx_modify_rq_attr rq_attr = { 0 };\n \tstruct mlx5_txq_ctrl *txq_ctrl;\n+\tstruct mlx5_rxq_priv *rxq;\n \tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \tstruct mlx5_devx_obj *sq;\n \tstruct mlx5_devx_obj *rq;\n@@ -259,9 +262,8 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tsq = txq_ctrl->obj->sq;\n-\t\trxq_ctrl = mlx5_rxq_get(dev,\n-\t\t\t\t\ttxq_ctrl->hairpin_conf.peers[0].queue);\n-\t\tif (!rxq_ctrl) {\n+\t\trxq = mlx5_rxq_get(dev, txq_ctrl->hairpin_conf.peers[0].queue);\n+\t\tif (rxq == NULL) {\n \t\t\tmlx5_txq_release(dev, i);\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u no rxq object found: %d\",\n@@ -269,6 +271,7 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)\n \t\t\t\ttxq_ctrl->hairpin_conf.peers[0].queue);\n \t\t\treturn -rte_errno;\n \t\t}\n+\t\trxq_ctrl = rxq->ctrl;\n \t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN ||\n \t\t rxq_ctrl->hairpin_conf.peers[0].queue != i) {\n \t\t\trte_errno = ENOMEM;\n@@ -303,12 +306,10 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)\n \t\trxq_ctrl->hairpin_status = 1;\n \t\ttxq_ctrl->hairpin_status = 1;\n \t\tmlx5_txq_release(dev, i);\n-\t\tmlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue);\n \t}\n \treturn 0;\n error:\n \tmlx5_txq_release(dev, i);\n-\tmlx5_rxq_release(dev, txq_ctrl->hairpin_conf.peers[0].queue);\n \treturn -rte_errno;\n }\n \n@@ -381,27 +382,26 @@ mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,\n \t\tpeer_info->manual_bind = txq_ctrl->hairpin_conf.manual_bind;\n \t\tmlx5_txq_release(dev, peer_queue);\n \t} else { /* Peer port used as ingress. */\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, peer_queue);\n \t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \n-\t\trxq_ctrl = mlx5_rxq_get(dev, peer_queue);\n-\t\tif (rxq_ctrl == NULL) {\n+\t\tif (rxq == NULL) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"Failed to get port %u Rx queue %d\",\n \t\t\t\tdev->data->port_id, peer_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n+\t\trxq_ctrl = rxq->ctrl;\n \t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u queue %d is not a hairpin Rxq\",\n \t\t\t\tdev->data->port_id, peer_queue);\n-\t\t\tmlx5_rxq_release(dev, peer_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tif (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {\n \t\t\trte_errno = ENOMEM;\n \t\t\tDRV_LOG(ERR, \"port %u no Rxq object found: %d\",\n \t\t\t\tdev->data->port_id, peer_queue);\n-\t\t\tmlx5_rxq_release(dev, peer_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tpeer_info->qp_id = rxq_ctrl->obj->rq->id;\n@@ -409,7 +409,6 @@ mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,\n \t\tpeer_info->peer_q = rxq_ctrl->hairpin_conf.peers[0].queue;\n \t\tpeer_info->tx_explicit = rxq_ctrl->hairpin_conf.tx_explicit;\n \t\tpeer_info->manual_bind = rxq_ctrl->hairpin_conf.manual_bind;\n-\t\tmlx5_rxq_release(dev, peer_queue);\n \t}\n \treturn 0;\n }\n@@ -508,34 +507,32 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\t\ttxq_ctrl->hairpin_status = 1;\n \t\tmlx5_txq_release(dev, cur_queue);\n \t} else {\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, cur_queue);\n \t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \t\tstruct mlx5_devx_modify_rq_attr rq_attr = { 0 };\n \n-\t\trxq_ctrl = mlx5_rxq_get(dev, cur_queue);\n-\t\tif (rxq_ctrl == NULL) {\n+\t\tif (rxq == NULL) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"Failed to get port %u Rx queue %d\",\n \t\t\t\tdev->data->port_id, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n+\t\trxq_ctrl = rxq->ctrl;\n \t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u queue %d not a hairpin Rxq\",\n \t\t\t\tdev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tif (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {\n \t\t\trte_errno = ENOMEM;\n \t\t\tDRV_LOG(ERR, \"port %u no Rxq object found: %d\",\n \t\t\t\tdev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tif (rxq_ctrl->hairpin_status != 0) {\n \t\t\tDRV_LOG(DEBUG, \"port %u Rx queue %d is already bound\",\n \t\t\t\tdev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn 0;\n \t\t}\n \t\tif (peer_info->tx_explicit !=\n@@ -543,7 +540,6 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u Rx queue %d and peer Tx rule mode\"\n \t\t\t\t\" mismatch\", dev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tif (peer_info->manual_bind !=\n@@ -551,7 +547,6 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u Rx queue %d and peer binding mode\"\n \t\t\t\t\" mismatch\", dev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\trq_attr.state = MLX5_SQC_STATE_RDY;\n@@ -561,7 +556,6 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\tret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);\n \t\tif (ret == 0)\n \t\t\trxq_ctrl->hairpin_status = 1;\n-\t\tmlx5_rxq_release(dev, cur_queue);\n \t}\n \treturn ret;\n }\n@@ -626,34 +620,32 @@ mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\t\ttxq_ctrl->hairpin_status = 0;\n \t\tmlx5_txq_release(dev, cur_queue);\n \t} else {\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, cur_queue);\n \t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \t\tstruct mlx5_devx_modify_rq_attr rq_attr = { 0 };\n \n-\t\trxq_ctrl = mlx5_rxq_get(dev, cur_queue);\n-\t\tif (rxq_ctrl == NULL) {\n+\t\tif (rxq == NULL) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"Failed to get port %u Rx queue %d\",\n \t\t\t\tdev->data->port_id, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n+\t\trxq_ctrl = rxq->ctrl;\n \t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u queue %d not a hairpin Rxq\",\n \t\t\t\tdev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tif (rxq_ctrl->hairpin_status == 0) {\n \t\t\tDRV_LOG(DEBUG, \"port %u Rx queue %d is already unbound\",\n \t\t\t\tdev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn 0;\n \t\t}\n \t\tif (rxq_ctrl->obj == NULL || rxq_ctrl->obj->rq == NULL) {\n \t\t\trte_errno = ENOMEM;\n \t\t\tDRV_LOG(ERR, \"port %u no Rxq object found: %d\",\n \t\t\t\tdev->data->port_id, cur_queue);\n-\t\t\tmlx5_rxq_release(dev, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\trq_attr.state = MLX5_SQC_STATE_RST;\n@@ -661,7 +653,6 @@ mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\tret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);\n \t\tif (ret == 0)\n \t\t\trxq_ctrl->hairpin_status = 0;\n-\t\tmlx5_rxq_release(dev, cur_queue);\n \t}\n \treturn ret;\n }\n@@ -963,7 +954,6 @@ mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_txq_ctrl *txq_ctrl;\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n \tuint32_t i;\n \tuint16_t pp;\n \tuint32_t bits[(RTE_MAX_ETHPORTS + 31) / 32] = {0};\n@@ -992,24 +982,23 @@ mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,\n \t\t}\n \t} else {\n \t\tfor (i = 0; i < priv->rxqs_n; i++) {\n-\t\t\trxq_ctrl = mlx5_rxq_get(dev, i);\n-\t\t\tif (!rxq_ctrl)\n+\t\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i);\n+\t\t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n+\n+\t\t\tif (rxq == NULL)\n \t\t\t\tcontinue;\n-\t\t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) {\n-\t\t\t\tmlx5_rxq_release(dev, i);\n+\t\t\trxq_ctrl = rxq->ctrl;\n+\t\t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN)\n \t\t\t\tcontinue;\n-\t\t\t}\n \t\t\tpp = rxq_ctrl->hairpin_conf.peers[0].port;\n \t\t\tif (pp >= RTE_MAX_ETHPORTS) {\n \t\t\t\trte_errno = ERANGE;\n-\t\t\t\tmlx5_rxq_release(dev, i);\n \t\t\t\tDRV_LOG(ERR, \"port %hu queue %u peer port \"\n \t\t\t\t\t\"out of range %hu\",\n \t\t\t\t\tpriv->dev_data->port_id, i, pp);\n \t\t\t\treturn -rte_errno;\n \t\t\t}\n \t\t\tbits[pp / 32] |= 1 << (pp % 32);\n-\t\t\tmlx5_rxq_release(dev, i);\n \t\t}\n \t}\n \tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n", "prefixes": [ "06/11" ] }