diff mbox series

[13/18] common/idpf: replace MAKEMASK to IDPF_M

Message ID 20230413094502.1714755-14-wenjing.qiao@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series update idpf shared code |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Wenjing Qiao April 13, 2023, 9:44 a.m. UTC 
  Replace MAKEMASK to IDPF_M to avoid conflicts with MAKEMASK
redefinition from various subcomponents.

Signed-off-by: Priyalee Kushwaha <priyalee.kushwaha@intel.com>
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
 drivers/common/idpf/base/idpf_controlq.h      |  3 --
 drivers/common/idpf/base/idpf_lan_pf_regs.h   | 26 +++++------
 drivers/common/idpf/base/idpf_lan_txrx.h      | 46 +++++++++----------
 drivers/common/idpf/base/idpf_lan_vf_regs.h   | 16 +++----
 drivers/common/idpf/base/idpf_osdep.h         |  2 +
 drivers/common/idpf/base/idpf_type.h          |  2 -
 drivers/common/idpf/base/virtchnl2_lan_desc.h | 28 +++++------
 7 files changed, 60 insertions(+), 63 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/idpf/base/idpf_controlq.h b/drivers/common/idpf/base/idpf_controlq.h
index e7b0d803b3..47bffcf79f 100644
--- a/drivers/common/idpf/base/idpf_controlq.h
+++ b/drivers/common/idpf/base/idpf_controlq.h
@@ -97,9 +97,6 @@  struct idpf_ctlq_desc {
 #define IDPF_CTLQ_FLAG_VFC	BIT(IDPF_CTLQ_FLAG_VFC_S)	/* 0x800  */
 #define IDPF_CTLQ_FLAG_BUF	BIT(IDPF_CTLQ_FLAG_BUF_S)	/* 0x1000 */
 
-/* Host ID is a special field that has 3b and not a 1b flag */
-#define IDPF_CTLQ_FLAG_HOST_ID_M MAKE_MASK(0x7000UL, IDPF_CTLQ_FLAG_HOST_ID_S)
-
 struct idpf_mbxq_desc {
 	u8 pad[8];		/* CTLQ flags/opcode/len/retval fields */
 	u32 chnl_opcode;	/* avoid confusion with desc->opcode */
diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h
index 7f731ec3d6..1c665d1f3b 100644
--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h
@@ -24,7 +24,7 @@ 
 #define PF_FW_ARQBAH			(PF_FW_BASE + 0x4)
 #define PF_FW_ARQLEN			(PF_FW_BASE + 0x8)
 #define PF_FW_ARQLEN_ARQLEN_S		0
-#define PF_FW_ARQLEN_ARQLEN_M		MAKEMASK(0x1FFF, PF_FW_ARQLEN_ARQLEN_S)
+#define PF_FW_ARQLEN_ARQLEN_M		IDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S)
 #define PF_FW_ARQLEN_ARQVFE_S		28
 #define PF_FW_ARQLEN_ARQVFE_M		BIT(PF_FW_ARQLEN_ARQVFE_S)
 #define PF_FW_ARQLEN_ARQOVFL_S		29
@@ -35,14 +35,14 @@ 
 #define PF_FW_ARQLEN_ARQENABLE_M	BIT(PF_FW_ARQLEN_ARQENABLE_S)
 #define PF_FW_ARQH			(PF_FW_BASE + 0xC)
 #define PF_FW_ARQH_ARQH_S		0
-#define PF_FW_ARQH_ARQH_M		MAKEMASK(0x1FFF, PF_FW_ARQH_ARQH_S)
+#define PF_FW_ARQH_ARQH_M		IDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S)
 #define PF_FW_ARQT			(PF_FW_BASE + 0x10)
 
 #define PF_FW_ATQBAL			(PF_FW_BASE + 0x14)
 #define PF_FW_ATQBAH			(PF_FW_BASE + 0x18)
 #define PF_FW_ATQLEN			(PF_FW_BASE + 0x1C)
 #define PF_FW_ATQLEN_ATQLEN_S		0
-#define PF_FW_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, PF_FW_ATQLEN_ATQLEN_S)
+#define PF_FW_ATQLEN_ATQLEN_M		IDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)
 #define PF_FW_ATQLEN_ATQVFE_S		28
 #define PF_FW_ATQLEN_ATQVFE_M		BIT(PF_FW_ATQLEN_ATQVFE_S)
 #define PF_FW_ATQLEN_ATQOVFL_S		29
@@ -53,7 +53,7 @@ 
 #define PF_FW_ATQLEN_ATQENABLE_M	BIT(PF_FW_ATQLEN_ATQENABLE_S)
 #define PF_FW_ATQH			(PF_FW_BASE + 0x20)
 #define PF_FW_ATQH_ATQH_S		0
-#define PF_FW_ATQH_ATQH_M		MAKEMASK(0x3FF, PF_FW_ATQH_ATQH_S)
+#define PF_FW_ATQH_ATQH_M		IDPF_M(0x3FF, PF_FW_ATQH_ATQH_S)
 #define PF_FW_ATQT			(PF_FW_BASE + 0x24)
 
 /* Interrupts */
@@ -66,7 +66,7 @@ 
 #define PF_GLINT_DYN_CTL_SWINT_TRIG_S	2
 #define PF_GLINT_DYN_CTL_SWINT_TRIG_M	BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S)
 #define PF_GLINT_DYN_CTL_ITR_INDX_S	3
-#define PF_GLINT_DYN_CTL_ITR_INDX_M	MAKEMASK(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S)
+#define PF_GLINT_DYN_CTL_ITR_INDX_M	IDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S)
 #define PF_GLINT_DYN_CTL_INTERVAL_S	5
 #define PF_GLINT_DYN_CTL_INTERVAL_M	BIT(PF_GLINT_DYN_CTL_INTERVAL_S)
 #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S	24
@@ -86,13 +86,13 @@ 
 #define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))
 #define PF_GLINT_ITR_MAX_INDEX		2
 #define PF_GLINT_ITR_INTERVAL_S		0
-#define PF_GLINT_ITR_INTERVAL_M		MAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S)
+#define PF_GLINT_ITR_INTERVAL_M		IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S)
 
 /* Timesync registers */
 #define PF_TIMESYNC_BASE		0x08404000
 #define PF_GLTSYN_CMD_SYNC		(PF_TIMESYNC_BASE)
 #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S	0
-#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M	MAKEMASK(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S)
+#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M	IDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S)
 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S	2
 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M	BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S)
 #define PF_GLTSYN_SHTIME_0		(PF_TIMESYNC_BASE + 0x4)
@@ -104,23 +104,23 @@ 
 /* Generic registers */
 #define PF_INT_DIR_OICR_ENA		0x08406000
 #define PF_INT_DIR_OICR_ENA_S		0
-#define PF_INT_DIR_OICR_ENA_M	MAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S)
+#define PF_INT_DIR_OICR_ENA_M	IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S)
 #define PF_INT_DIR_OICR			0x08406004
 #define PF_INT_DIR_OICR_TSYN_EVNT	0
 #define PF_INT_DIR_OICR_PHY_TS_0	BIT(1)
 #define PF_INT_DIR_OICR_PHY_TS_1	BIT(2)
 #define PF_INT_DIR_OICR_CAUSE		0x08406008
 #define PF_INT_DIR_OICR_CAUSE_CAUSE_S	0
-#define PF_INT_DIR_OICR_CAUSE_CAUSE_M	MAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S)
+#define PF_INT_DIR_OICR_CAUSE_CAUSE_M	IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S)
 #define PF_INT_PBA_CLEAR		0x0840600C
 
 #define PF_FUNC_RID			0x08406010
 #define PF_FUNC_RID_FUNCTION_NUMBER_S	0
-#define PF_FUNC_RID_FUNCTION_NUMBER_M	MAKEMASK(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S)
+#define PF_FUNC_RID_FUNCTION_NUMBER_M	IDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S)
 #define PF_FUNC_RID_DEVICE_NUMBER_S	3
-#define PF_FUNC_RID_DEVICE_NUMBER_M	MAKEMASK(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S)
+#define PF_FUNC_RID_DEVICE_NUMBER_M	IDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S)
 #define PF_FUNC_RID_BUS_NUMBER_S	8
-#define PF_FUNC_RID_BUS_NUMBER_M	MAKEMASK(0xFF, PF_FUNC_RID_BUS_NUMBER_S)
+#define PF_FUNC_RID_BUS_NUMBER_M	IDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S)
 
 /* Reset registers */
 #define PFGEN_RTRIG			0x08407000
@@ -132,7 +132,7 @@ 
 #define PFGEN_RTRIG_IMCR_M		BIT(2)
 #define PFGEN_RSTAT			0x08407008 /* PFR Status */
 #define PFGEN_RSTAT_PFR_STATE_S		0
-#define PFGEN_RSTAT_PFR_STATE_M		MAKEMASK(0x3, PFGEN_RSTAT_PFR_STATE_S)
+#define PFGEN_RSTAT_PFR_STATE_M		IDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S)
 #define PFGEN_CTRL			0x0840700C
 #define PFGEN_CTRL_PFSWR		BIT(0)
 
diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h
index 98484b267c..82742857be 100644
--- a/drivers/common/idpf/base/idpf_lan_txrx.h
+++ b/drivers/common/idpf/base/idpf_lan_txrx.h
@@ -68,9 +68,9 @@  enum idpf_rss_hash {
 #define IDPF_TXD_COMPLQ_GEN_M		BIT_ULL(IDPF_TXD_COMPLQ_GEN_S)
 #define IDPF_TXD_COMPLQ_COMPL_TYPE_S	11
 #define IDPF_TXD_COMPLQ_COMPL_TYPE_M	\
-	MAKEMASK(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S)
+	IDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S)
 #define IDPF_TXD_COMPLQ_QID_S	0
-#define IDPF_TXD_COMPLQ_QID_M		MAKEMASK(0x3FFUL, IDPF_TXD_COMPLQ_QID_S)
+#define IDPF_TXD_COMPLQ_QID_M		IDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S)
 
 /* For base mode TX descriptors */
 
@@ -100,29 +100,29 @@  enum idpf_rss_hash {
 
 #define IDPF_TXD_CTX_QW1_MSS_S		50
 #define IDPF_TXD_CTX_QW1_MSS_M		\
-	MAKEMASK(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S)
+	IDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S)
 #define IDPF_TXD_CTX_QW1_TSO_LEN_S	30
 #define IDPF_TXD_CTX_QW1_TSO_LEN_M	\
-	MAKEMASK(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S)
+	IDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S)
 #define IDPF_TXD_CTX_QW1_CMD_S		4
 #define IDPF_TXD_CTX_QW1_CMD_M		\
-	MAKEMASK(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S)
+	IDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S)
 #define IDPF_TXD_CTX_QW1_DTYPE_S	0
 #define IDPF_TXD_CTX_QW1_DTYPE_M	\
-	MAKEMASK(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S)
+	IDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S)
 #define IDPF_TXD_QW1_L2TAG1_S		48
 #define IDPF_TXD_QW1_L2TAG1_M		\
-	MAKEMASK(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S)
+	IDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S)
 #define IDPF_TXD_QW1_TX_BUF_SZ_S	34
 #define IDPF_TXD_QW1_TX_BUF_SZ_M	\
-	MAKEMASK(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S)
+	IDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S)
 #define IDPF_TXD_QW1_OFFSET_S		16
 #define IDPF_TXD_QW1_OFFSET_M		\
-	MAKEMASK(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S)
+	IDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S)
 #define IDPF_TXD_QW1_CMD_S		4
-#define IDPF_TXD_QW1_CMD_M		MAKEMASK(0xFFFUL, IDPF_TXD_QW1_CMD_S)
+#define IDPF_TXD_QW1_CMD_M		IDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S)
 #define IDPF_TXD_QW1_DTYPE_S		0
-#define IDPF_TXD_QW1_DTYPE_M		MAKEMASK(0xFUL, IDPF_TXD_QW1_DTYPE_S)
+#define IDPF_TXD_QW1_DTYPE_M		IDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S)
 
 /* TX Completion Descriptor Completion Types */
 #define IDPF_TXD_COMPLT_ITR_FLUSH	0
@@ -173,10 +173,10 @@  enum idpf_tx_desc_len_fields {
 	IDPF_TX_DESC_LEN_L4_LEN_S	= 14 /* 4 BITS */
 };
 
-#define IDPF_TXD_QW1_MACLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S)
-#define IDPF_TXD_QW1_IPLEN_M  MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S)
-#define IDPF_TXD_QW1_L4LEN_M  MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)
-#define IDPF_TXD_QW1_FCLEN_M  MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)
+#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S)
+#define IDPF_TXD_QW1_IPLEN_M  IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S)
+#define IDPF_TXD_QW1_L4LEN_M  IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)
+#define IDPF_TXD_QW1_FCLEN_M  IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)
 
 enum idpf_tx_base_desc_cmd_bits {
 	IDPF_TX_DESC_CMD_EOP			= 0x0001,
@@ -244,9 +244,9 @@  struct idpf_flex_tx_desc {
 		__le16 cmd_dtype;
 #define IDPF_FLEX_TXD_QW1_DTYPE_S		0
 #define IDPF_FLEX_TXD_QW1_DTYPE_M		\
-		MAKEMASK(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S)
+		IDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S)
 #define IDPF_FLEX_TXD_QW1_CMD_S		5
-#define IDPF_FLEX_TXD_QW1_CMD_M		MAKEMASK(0x7FFUL, IDPF_TXD_QW1_CMD_S)
+#define IDPF_FLEX_TXD_QW1_CMD_M		IDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S)
 		union {
 			/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */
 			u8 raw[4];
@@ -388,9 +388,9 @@  struct idpf_flex_tx_hs_ctx_desc {
 #define IDPF_TXD_FLEX_CTX_MSS_RT_0	0
 #define IDPF_TXD_FLEX_CTX_MSS_RT_M	0x3FFF
 #define IDPF_TXD_FLEX_CTX_FTYPE_S	14
-#define IDPF_TXD_FLEX_CTX_FTYPE_VF	MAKEMASK(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S)
-#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV	MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S)
-#define IDPF_TXD_FLEX_CTX_FTYPE_PF	MAKEMASK(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S)
+#define IDPF_TXD_FLEX_CTX_FTYPE_VF	IDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S)
+#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV	IDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S)
+#define IDPF_TXD_FLEX_CTX_FTYPE_PF	IDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S)
 			u8 hdr_len;
 			u8 ptag;
 		} tso;
@@ -407,10 +407,10 @@  struct idpf_flex_tx_hs_ctx_desc {
 #define IDPF_TXD_FLEX_CTX_QW1_PASID_M		0xFFFFF
 #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S	36
 #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID	\
-		MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S)
+		IDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S)
 #define IDPF_TXD_FLEX_CTX_QW1_TPH_S		37
 #define IDPF_TXD_FLEX_CTX_QW1_TPH \
-		MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_TPH_S)
+		IDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S)
 #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S		38
 #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M		0xF
 /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */
@@ -418,7 +418,7 @@  struct idpf_flex_tx_hs_ctx_desc {
 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M		0x1FFFFF
 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S	63
 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID	\
-		MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)
+		IDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)
 /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */
 #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S		48
 #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M		0xFF
diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h
index 13c5c5a7da..c8739fae7a 100644
--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h
@@ -9,7 +9,7 @@ 
 /* Reset */
 #define VFGEN_RSTAT			0x00008800
 #define VFGEN_RSTAT_VFR_STATE_S		0
-#define VFGEN_RSTAT_VFR_STATE_M		MAKEMASK(0x3, VFGEN_RSTAT_VFR_STATE_S)
+#define VFGEN_RSTAT_VFR_STATE_M		IDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S)
 
 /* Control(VF Mailbox) Queue */
 #define VF_BASE				0x00006000
@@ -18,7 +18,7 @@ 
 #define VF_ATQBAH			(VF_BASE + 0x1800)
 #define VF_ATQLEN			(VF_BASE + 0x0800)
 #define VF_ATQLEN_ATQLEN_S		0
-#define VF_ATQLEN_ATQLEN_M		MAKEMASK(0x3FF, VF_ATQLEN_ATQLEN_S)
+#define VF_ATQLEN_ATQLEN_M		IDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S)
 #define VF_ATQLEN_ATQVFE_S		28
 #define VF_ATQLEN_ATQVFE_M		BIT(VF_ATQLEN_ATQVFE_S)
 #define VF_ATQLEN_ATQOVFL_S		29
@@ -29,14 +29,14 @@ 
 #define VF_ATQLEN_ATQENABLE_M		BIT(VF_ATQLEN_ATQENABLE_S)
 #define VF_ATQH				(VF_BASE + 0x0400)
 #define VF_ATQH_ATQH_S			0
-#define VF_ATQH_ATQH_M			MAKEMASK(0x3FF, VF_ATQH_ATQH_S)
+#define VF_ATQH_ATQH_M			IDPF_M(0x3FF, VF_ATQH_ATQH_S)
 #define VF_ATQT				(VF_BASE + 0x2400)
 
 #define VF_ARQBAL			(VF_BASE + 0x0C00)
 #define VF_ARQBAH			(VF_BASE)
 #define VF_ARQLEN			(VF_BASE + 0x2000)
 #define VF_ARQLEN_ARQLEN_S		0
-#define VF_ARQLEN_ARQLEN_M		MAKEMASK(0x3FF, VF_ARQLEN_ARQLEN_S)
+#define VF_ARQLEN_ARQLEN_M		IDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S)
 #define VF_ARQLEN_ARQVFE_S		28
 #define VF_ARQLEN_ARQVFE_M		BIT(VF_ARQLEN_ARQVFE_S)
 #define VF_ARQLEN_ARQOVFL_S		29
@@ -47,7 +47,7 @@ 
 #define VF_ARQLEN_ARQENABLE_M		BIT(VF_ARQLEN_ARQENABLE_S)
 #define VF_ARQH				(VF_BASE + 0x1400)
 #define VF_ARQH_ARQH_S			0
-#define VF_ARQH_ARQH_M			MAKEMASK(0x1FFF, VF_ARQH_ARQH_S)
+#define VF_ARQH_ARQH_M			IDPF_M(0x1FFF, VF_ARQH_ARQH_S)
 #define VF_ARQT				(VF_BASE + 0x1000)
 
 /* Transmit queues */
@@ -69,7 +69,7 @@ 
 #define VF_INT_DYN_CTL0_INTENA_S	0
 #define VF_INT_DYN_CTL0_INTENA_M	BIT(VF_INT_DYN_CTL0_INTENA_S)
 #define VF_INT_DYN_CTL0_ITR_INDX_S	3
-#define VF_INT_DYN_CTL0_ITR_INDX_M	MAKEMASK(0x3, VF_INT_DYN_CTL0_ITR_INDX_S)
+#define VF_INT_DYN_CTL0_ITR_INDX_M	IDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S)
 #define VF_INT_DYN_CTLN(_INT)		(0x00003800 + ((_INT) * 4))
 #define VF_INT_DYN_CTLN_EXT(_INT)	(0x00070000 + ((_INT) * 4))
 #define VF_INT_DYN_CTLN_INTENA_S	0
@@ -79,7 +79,7 @@ 
 #define VF_INT_DYN_CTLN_SWINT_TRIG_S	2
 #define VF_INT_DYN_CTLN_SWINT_TRIG_M	BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S)
 #define VF_INT_DYN_CTLN_ITR_INDX_S	3
-#define VF_INT_DYN_CTLN_ITR_INDX_M	MAKEMASK(0x3, VF_INT_DYN_CTLN_ITR_INDX_S)
+#define VF_INT_DYN_CTLN_ITR_INDX_M	IDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S)
 #define VF_INT_DYN_CTLN_INTERVAL_S	5
 #define VF_INT_DYN_CTLN_INTERVAL_M	BIT(VF_INT_DYN_CTLN_INTERVAL_S)
 #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S	24
@@ -104,7 +104,7 @@ 
 #define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))
 #define VF_INT_ITRN_MAX_INDEX		2
 #define VF_INT_ITRN_INTERVAL_S		0
-#define VF_INT_ITRN_INTERVAL_M		MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)
+#define VF_INT_ITRN_INTERVAL_M		IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S)
 #define VF_INT_PBA_CLEAR		0x00008900
 
 #define VF_INT_ICR0_ENA1		0x00005000
diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h
index 99ae9cf60a..abcf68f1a2 100644
--- a/drivers/common/idpf/base/idpf_osdep.h
+++ b/drivers/common/idpf/base/idpf_osdep.h
@@ -45,6 +45,8 @@  typedef struct idpf_lock idpf_lock;
 #define low_16_bits(x)		((x) & 0xFFFF)
 #define high_16_bits(x)		(((x) & 0xFFFF0000) >> 16)
 
+#define IDPF_M(m, s)		((m) << (s))
+
 #ifndef ETH_ADDR_LEN
 #define ETH_ADDR_LEN		6
 #endif
diff --git a/drivers/common/idpf/base/idpf_type.h b/drivers/common/idpf/base/idpf_type.h
index 3b46536287..2a97d32a8b 100644
--- a/drivers/common/idpf/base/idpf_type.h
+++ b/drivers/common/idpf/base/idpf_type.h
@@ -14,8 +14,6 @@ 
 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)
 
-#define MAKEMASK(m, s)	((m) << (s))
-
 struct idpf_eth_stats {
 	u64 rx_bytes;			/* gorc */
 	u64 rx_unicast;			/* uprc */
diff --git a/drivers/common/idpf/base/virtchnl2_lan_desc.h b/drivers/common/idpf/base/virtchnl2_lan_desc.h
index b8cb22e474..0992cefc6c 100644
--- a/drivers/common/idpf/base/virtchnl2_lan_desc.h
+++ b/drivers/common/idpf/base/virtchnl2_lan_desc.h
@@ -80,19 +80,19 @@ 
 /* For splitq virtchnl2_rx_flex_desc_adv desc members */
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S		0
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M		\
-	MAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S)
+	IDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S		0
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M		\
-	MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S)
+	IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S		10
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M		\
-	MAKEMASK(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S)
+	IDPF_M(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S		12
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M			\
-	MAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S)
+	IDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S		0
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M	\
-	MAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S)
+	IDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S		14
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M			\
 	BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S)
@@ -101,7 +101,7 @@ 
 	BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S		0
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M		\
-	MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S)
+	IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S		10
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M			\
 	BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S)
@@ -110,7 +110,7 @@ 
 	BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S		12
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M			\
-	MAKEMASK(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M)
+	IDPF_M(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M)
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S		15
 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M		\
 	BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S)
@@ -159,12 +159,12 @@ 
 /* for virtchnl2_rx_flex_desc.ptype_flex_flags0 member */
 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_S			0
 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M			\
-	MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */
+	IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */
 
 /* for virtchnl2_rx_flex_desc.pkt_length member */
 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S			0
 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M			\
-	MAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */
+	IDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */
 
 /* VIRTCHNL2_RX_FLEX_DESC_STATUS_ERROR_0_BITS
  * for singleq (flex) virtchnl2_rx_flex_desc
@@ -212,19 +212,19 @@ 
 	BIT_ULL(VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S)
 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S	52
 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_M	\
-	MAKEMASK(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S)
+	IDPF_M(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S)
 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S	38
 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M	\
-	MAKEMASK(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S)
+	IDPF_M(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S)
 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S	30
 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M	\
-	MAKEMASK(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S)
+	IDPF_M(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S)
 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S	19
 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M	\
-	MAKEMASK(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S)
+	IDPF_M(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S)
 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S	0
 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M	\
-	MAKEMASK(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S)
+	IDPF_M(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S)
 
 /* VIRTCHNL2_RX_BASE_DESC_STATUS_BITS
  * for singleq (base) virtchnl2_rx_base_desc