diff mbox series

[V1,3/5] net/mlx5: support VXLAN-GPE reserved fields matching

Message ID 20240112080210.1288356-4-gavinl@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series support VXLAN-GPE header fields(flags, rsvd0 and rsvd1) matching |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Gavin Li Jan. 12, 2024, 8:02 a.m. UTC 
  This adds matching on the reserved fields of VXLAN-GPE header (the 16-bits
before Next Protocol and the last 8-bits).

To support all the header fields, tunnel_header_0_1 should be supported by
FW and misc5_cap is set.

If one of the reserved fields is matched on, misc5 is used for matching.
Otherwise, keep using misc3

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 doc/guides/nics/mlx5.rst        |  5 +++++
 drivers/net/mlx5/mlx5_flow.c    |  5 +++++
 drivers/net/mlx5/mlx5_flow_dv.c | 32 ++++++++++++++++++++++++++------
 3 files changed, 36 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 7bfd6c6aeb..27384d5a86 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -311,6 +311,11 @@  Limitations
   Group zero's behavior may differ which depends on FW.
   Matching value equals 0 (value & mask) is not supported.
 
+- Matching on VXLAN-GPE header fields:
+
+     - ``rsvd0``/``rsvd1`` matching support depends on FW version when using DV flow
+       engine (``dv_flow_en`` = 1).
+
 - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.
 
 - MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2).
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index ffa183dc1b..9b6f483d3f 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -3316,6 +3316,11 @@  mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  "no outer UDP layer found");
 	if (!mask)
 		mask = &rte_flow_item_vxlan_gpe_mask;
+	if (priv->sh->misc5_cap && priv->sh->tunnel_header_0_1) {
+		nic_mask.rsvd0[0] = 0xff;
+		nic_mask.rsvd0[1] = 0xff;
+		nic_mask.rsvd1 = 0xff;
+	}
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
 		 (const uint8_t *)&nic_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 97f55003c3..f3589da654 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -9813,14 +9813,10 @@  flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item,
 		vxlan_v = vxlan_m;
 	else if (key_type == MLX5_SET_MATCHER_HS_V)
 		vxlan_m = vxlan_v;
-	for (i = 0; i < size; ++i)
-		vni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i];
 	if (vxlan_m->hdr.flags) {
 		flags_m = vxlan_m->hdr.flags;
 		flags_v = vxlan_v->hdr.flags;
 	}
-	MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags,
-		 flags_m & flags_v);
 	m_protocol = vxlan_m->hdr.protocol;
 	v_protocol = vxlan_v->hdr.protocol;
 	if (!m_protocol) {
@@ -9839,8 +9835,32 @@  flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item,
 		if (key_type & MLX5_SET_MATCHER_M)
 			v_protocol = m_protocol;
 	}
-	MLX5_SET(fte_match_set_misc3, misc_v,
-		 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
+	/*
+	 * If only match flags/protocol/vni field, keep using misc3 for matching.
+	 * If need to match rsvd0 or rsvd1, using misc5 and do not need using misc3.
+	 */
+	if (!(vxlan_m->hdr.rsvd0[0] || vxlan_m->hdr.rsvd0[1] || vxlan_m->hdr.rsvd1)) {
+		for (i = 0; i < size; ++i)
+			vni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i];
+		MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags,
+			 flags_m & flags_v);
+		MLX5_SET(fte_match_set_misc3, misc_v,
+			 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
+	} else {
+		uint32_t tunnel_v;
+		void *misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+
+		tunnel_v = (flags_m & flags_v) << 24 |
+			   (vxlan_v->hdr.rsvd0[0] & vxlan_m->hdr.rsvd0[0]) << 16 |
+			   (vxlan_v->hdr.rsvd0[1] & vxlan_m->hdr.rsvd0[1]) << 8 |
+			   (m_protocol & v_protocol);
+		MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0, tunnel_v);
+		tunnel_v = (vxlan_v->hdr.vni[0] & vxlan_m->hdr.vni[0]) << 24 |
+			   (vxlan_v->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 16 |
+			   (vxlan_v->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 8 |
+			   (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1);
+		MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1, tunnel_v);
+	}
 }
 
 /**