[v2,2/3] common/qat: add new QAT GEN3 definitions
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Commit Message
This patch adds few definitions specific to GEN3 QAT.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
drivers/common/qat/qat_adf/icp_qat_fw_la.h | 19 +++++++++++++++----
drivers/common/qat/qat_adf/icp_qat_hw.h | 19 +++++++++++++++++++
2 files changed, 34 insertions(+), 4 deletions(-)
Comments
> -----Original Message-----
> From: Dybkowski, AdamX
> Sent: Friday, September 27, 2019 4:48 PM
> To: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>; akhil.goyal@nxp.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH v2 2/3] common/qat: add new QAT GEN3 definitions
>
> This patch adds few definitions specific to GEN3 QAT.
>
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
- * Copyright(c) 2015-2018 Intel Corporation
+ * Copyright(c) 2015-2019 Intel Corporation
*/
#ifndef _ICP_QAT_FW_LA_H_
#define _ICP_QAT_FW_LA_H_
@@ -34,6 +34,9 @@ struct icp_qat_fw_la_bulk_req {
struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
};
+#define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS 13
+#define ICP_QAT_FW_LA_SINGLE_PASS_PROTO 1
+#define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK 0x1
#define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
#define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
@@ -152,6 +155,10 @@ struct icp_qat_fw_la_bulk_req {
QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
+#define ICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(flags, val) \
+ QAT_FIELD_SET(flags, val, QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS, \
+ QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK)
+
#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \
QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
QAT_LA_GCM_IV_LEN_FLAG_MASK)
@@ -267,8 +274,7 @@ struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
#define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0
#define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX 240
-#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \
- (sizeof(struct icp_qat_fw_la_cipher_req_params_t))
+#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET 24
#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
struct icp_qat_fw_la_cipher_req_params {
@@ -281,7 +287,12 @@ struct icp_qat_fw_la_cipher_req_params {
uint64_t resrvd1;
} s;
} u;
-};
+ uint64_t spc_aad_addr;
+ uint64_t spc_auth_res_addr;
+ uint16_t spc_aad_sz;
+ uint8_t reserved;
+ uint8_t spc_auth_res_sz;
+} __rte_packed;
struct icp_qat_fw_la_auth_req_params {
uint32_t auth_off;
@@ -212,6 +212,7 @@ enum icp_qat_hw_cipher_mode {
ICP_QAT_HW_CIPHER_CBC_MODE = 1,
ICP_QAT_HW_CIPHER_CTR_MODE = 2,
ICP_QAT_HW_CIPHER_F8_MODE = 3,
+ ICP_QAT_HW_CIPHER_AEAD_MODE = 4,
ICP_QAT_HW_CIPHER_XTS_MODE = 6,
ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
};
@@ -244,6 +245,8 @@ enum icp_qat_hw_cipher_convert {
#define QAT_CIPHER_CONVERT_MASK 0x1
#define QAT_CIPHER_DIR_BITPOS 8
#define QAT_CIPHER_DIR_MASK 0x1
+#define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10
+#define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F
#define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
#define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
#define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
@@ -251,6 +254,22 @@ enum icp_qat_hw_cipher_convert {
((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
+
+#define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24
+#define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8
+#define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF
+#define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F
+#define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16
+#define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \
+ ({ \
+ typeof(aad_size) aad_size1 = aad_size; \
+ (((((aad_size1) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \
+ QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) << \
+ QAT_CIPHER_AEAD_AAD_SIZE_BITPOS) | \
+ (((aad_size1) & QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK) << \
+ QAT_CIPHER_AEAD_AAD_LOWER_SHIFT)); \
+ })
+
#define ICP_QAT_HW_DES_BLK_SZ 8
#define ICP_QAT_HW_3DES_BLK_SZ 8
#define ICP_QAT_HW_NULL_BLK_SZ 8