diff mbox series

[2/2] net/mlx5: add support for more tunnel types

Message ID 20210913142535.9084-2-elibr@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Ferruh Yigit
Headers
Series [1/2] app/testpmd: add tunnel types |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/github-robot: build success github build: passed
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing fail Testing issues
ci/iol-intel-Performance success Performance Testing PASS

Commit Message

Eli Britstein Sept. 13, 2021, 2:25 p.m. UTC 
  Accept RTE_FLOW_ITEM_TYPE_GRE, RTE_FLOW_ITEM_TYPE_NVGRE and
RTE_FLOW_ITEM_TYPE_GENEVE as valid tunnel types.

Signed-off-by: Eli Britstein <elibr@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Slava Ovsiienko Oct. 18, 2021, 8:48 a.m. UTC | #1 
> -----Original Message-----
> From: Eli Britstein <elibr@nvidia.com>
> Sent: Monday, September 13, 2021 17:26
> To: dev@dpdk.org
> Cc: xiaoyun.li@intel.com; Matan Azrad <matan@nvidia.com>; Shahaf Shuler
> <shahafs@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>; Gregory
> Etelson <getelson@nvidia.com>; Eli Britstein <elibr@nvidia.com>
> Subject: [PATCH 2/2] net/mlx5: add support for more tunnel types
> 
> Accept RTE_FLOW_ITEM_TYPE_GRE, RTE_FLOW_ITEM_TYPE_NVGRE and
> RTE_FLOW_ITEM_TYPE_GENEVE as valid tunnel types.
> 
> Signed-off-by: Eli Britstein <elibr@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 4762fa0f5f..a2810c4be3 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -9099,6 +9099,9 @@  mlx5_flow_tunnel_validate(struct rte_eth_dev *dev,
 		err_msg = "unsupported tunnel type";
 		goto out;
 	case RTE_FLOW_ITEM_TYPE_VXLAN:
+	case RTE_FLOW_ITEM_TYPE_GRE:
+	case RTE_FLOW_ITEM_TYPE_NVGRE:
+	case RTE_FLOW_ITEM_TYPE_GENEVE:
 		break;
 	}