[v2] eal: add notes to SMP memory barrier APIs
Checks
Commit Message
The rte_smp_xx() APIs are deprecated. But it is not mentioned
in the function header.
Added notes in function header for clarification.
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
v2: Made the notes more specific.
lib/eal/include/generic/rte_atomic.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Comments
On 2023-06-26 09:12, Ruifeng Wang wrote:
> The rte_smp_xx() APIs are deprecated. But it is not mentioned
> in the function header.
> Added notes in function header for clarification.
>
> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> ---
> v2: Made the notes more specific.
>
> lib/eal/include/generic/rte_atomic.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/lib/eal/include/generic/rte_atomic.h b/lib/eal/include/generic/rte_atomic.h
> index 58df843c54..35e0041ce6 100644
> --- a/lib/eal/include/generic/rte_atomic.h
> +++ b/lib/eal/include/generic/rte_atomic.h
> @@ -55,6 +55,11 @@ static inline void rte_rmb(void);
> * Guarantees that the LOAD and STORE operations that precede the
> * rte_smp_mb() call are globally visible across the lcores
> * before the LOAD and STORE operations that follows it.
> + *
> + * @note
> + * This function is deprecated. It provides fence synchronization
> + * primitive but doesn't take memory order parameter.
> + * rte_atomic_thread_fence() should be used instead.
I can't see why coding the memory model semantics into the name, rather
than by specification-by-means-of-a-parameter, could be the real issue.
Could you explain? Seems like just different syntax to me.
The old <rte_atomic.h> atomic arithmetic and atomic load/store
operations suffered from unspecified semantics in regards to any
ordering they imposed on other memory accesses. I guess that shortcoming
could be described as a "missing parameter", although that too would be
misleading. Unclear semantics seems not be the case for the kernel-style
barriers though.
> */
> static inline void rte_smp_mb(void);
>
> @@ -64,6 +69,11 @@ static inline void rte_smp_mb(void);
> * Guarantees that the STORE operations that precede the
> * rte_smp_wmb() call are globally visible across the lcores
> * before the STORE operations that follows it.
> + *
> + * @note
> + * This function is deprecated. It provides fence synchronization
> + * primitive but doesn't take memory order parameter.
> + * rte_atomic_thread_fence() should be used instead.
> */
> static inline void rte_smp_wmb(void);
>
> @@ -73,6 +83,11 @@ static inline void rte_smp_wmb(void);
> * Guarantees that the LOAD operations that precede the
> * rte_smp_rmb() call are globally visible across the lcores
> * before the LOAD operations that follows it.
> + *
> + * @note
> + * This function is deprecated. It provides fence synchronization
> + * primitive but doesn't take memory order parameter.
> + * rte_atomic_thread_fence() should be used instead.
> */
> static inline void rte_smp_rmb(void);
> ///@}
> @@ -122,6 +137,10 @@ static inline void rte_io_rmb(void);
>
> /**
> * Synchronization fence between threads based on the specified memory order.
> + *
> + * @param memorder
> + * The memory order defined by compiler atomic builtin at:
> + * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
> */
> static inline void rte_atomic_thread_fence(int memorder);
>
> -----Original Message-----
> From: Mattias Rönnblom <hofors@lysator.liu.se>
> Sent: Friday, June 30, 2023 3:44 AM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net; david.marchand@redhat.com
> Cc: dev@dpdk.org; roretzla@linux.microsoft.com; konstantin.v.ananyev@yandex.ru; Honnappa
> Nagarahalli <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>
> Subject: Re: [PATCH v2] eal: add notes to SMP memory barrier APIs
>
> On 2023-06-26 09:12, Ruifeng Wang wrote:
> > The rte_smp_xx() APIs are deprecated. But it is not mentioned in the
> > function header.
> > Added notes in function header for clarification.
> >
> > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > ---
> > v2: Made the notes more specific.
> >
> > lib/eal/include/generic/rte_atomic.h | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/lib/eal/include/generic/rte_atomic.h
> > b/lib/eal/include/generic/rte_atomic.h
> > index 58df843c54..35e0041ce6 100644
> > --- a/lib/eal/include/generic/rte_atomic.h
> > +++ b/lib/eal/include/generic/rte_atomic.h
> > @@ -55,6 +55,11 @@ static inline void rte_rmb(void);
> > * Guarantees that the LOAD and STORE operations that precede the
> > * rte_smp_mb() call are globally visible across the lcores
> > * before the LOAD and STORE operations that follows it.
> > + *
> > + * @note
> > + * This function is deprecated. It provides fence synchronization
> > + * primitive but doesn't take memory order parameter.
> > + * rte_atomic_thread_fence() should be used instead.
>
> I can't see why coding the memory model semantics into the name, rather than by
> specification-by-means-of-a-parameter, could be the real issue.
> Could you explain? Seems like just different syntax to me.
Yes, rte_smp_xx and rte_atomic_thread_fence have different syntaxes.
The compiler atomic builtins were accepted for memory ordering. It comprises atomic arithmetic,
atomic load/store, and atomic fence. It is simpler and clearer to do memory ordering by using
the atomic builtins whenever possible.
rte_smp_xx has functionality overlap with atomic fence builtins but with different memory model
semantics and different syntaxes. Because of the differences, it will make memory ordering a little
more complex if rte_smp_xx is kept aside atomic builtins suite.
>
> The old <rte_atomic.h> atomic arithmetic and atomic load/store operations suffered from
> unspecified semantics in regards to any ordering they imposed on other memory accesses. I
> guess that shortcoming could be described as a "missing parameter", although that too
> would be misleading. Unclear semantics seems not be the case for the kernel-style barriers
> though.
>
> > */
> > static inline void rte_smp_mb(void);
> >
> > @@ -64,6 +69,11 @@ static inline void rte_smp_mb(void);
> > * Guarantees that the STORE operations that precede the
> > * rte_smp_wmb() call are globally visible across the lcores
> > * before the STORE operations that follows it.
> > + *
> > + * @note
> > + * This function is deprecated. It provides fence synchronization
> > + * primitive but doesn't take memory order parameter.
> > + * rte_atomic_thread_fence() should be used instead.
> > */
> > static inline void rte_smp_wmb(void);
> >
> > @@ -73,6 +83,11 @@ static inline void rte_smp_wmb(void);
> > * Guarantees that the LOAD operations that precede the
> > * rte_smp_rmb() call are globally visible across the lcores
> > * before the LOAD operations that follows it.
> > + *
> > + * @note
> > + * This function is deprecated. It provides fence synchronization
> > + * primitive but doesn't take memory order parameter.
> > + * rte_atomic_thread_fence() should be used instead.
> > */
> > static inline void rte_smp_rmb(void);
> > ///@}
> > @@ -122,6 +137,10 @@ static inline void rte_io_rmb(void);
> >
> > /**
> > * Synchronization fence between threads based on the specified memory order.
> > + *
> > + * @param memorder
> > + * The memory order defined by compiler atomic builtin at:
> > + * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
> > */
> > static inline void rte_atomic_thread_fence(int memorder);
> >
On 2023-07-03 09:02, Ruifeng Wang wrote:
>> -----Original Message-----
>> From: Mattias Rönnblom <hofors@lysator.liu.se>
>> Sent: Friday, June 30, 2023 3:44 AM
>> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net; david.marchand@redhat.com
>> Cc: dev@dpdk.org; roretzla@linux.microsoft.com; konstantin.v.ananyev@yandex.ru; Honnappa
>> Nagarahalli <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>
>> Subject: Re: [PATCH v2] eal: add notes to SMP memory barrier APIs
>>
>> On 2023-06-26 09:12, Ruifeng Wang wrote:
>>> The rte_smp_xx() APIs are deprecated. But it is not mentioned in the
>>> function header.
>>> Added notes in function header for clarification.
>>>
>>> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
>>> ---
>>> v2: Made the notes more specific.
>>>
>>> lib/eal/include/generic/rte_atomic.h | 19 +++++++++++++++++++
>>> 1 file changed, 19 insertions(+)
>>>
>>> diff --git a/lib/eal/include/generic/rte_atomic.h
>>> b/lib/eal/include/generic/rte_atomic.h
>>> index 58df843c54..35e0041ce6 100644
>>> --- a/lib/eal/include/generic/rte_atomic.h
>>> +++ b/lib/eal/include/generic/rte_atomic.h
>>> @@ -55,6 +55,11 @@ static inline void rte_rmb(void);
>>> * Guarantees that the LOAD and STORE operations that precede the
>>> * rte_smp_mb() call are globally visible across the lcores
>>> * before the LOAD and STORE operations that follows it.
>>> + *
>>> + * @note
>>> + * This function is deprecated. It provides fence synchronization
>>> + * primitive but doesn't take memory order parameter.
>>> + * rte_atomic_thread_fence() should be used instead.
>>
>> I can't see why coding the memory model semantics into the name, rather than by
>> specification-by-means-of-a-parameter, could be the real issue.
>> Could you explain? Seems like just different syntax to me.
>
> Yes, rte_smp_xx and rte_atomic_thread_fence have different syntaxes.
>
> The compiler atomic builtins were accepted for memory ordering. It comprises atomic arithmetic,
> atomic load/store, and atomic fence. It is simpler and clearer to do memory ordering by using
> the atomic builtins whenever possible.
> rte_smp_xx has functionality overlap with atomic fence builtins but with different memory model
> semantics and different syntaxes. Because of the differences, it will make memory ordering a little
> more complex if rte_smp_xx is kept aside atomic builtins suite.
>
I wasn't arguing for keeping Linux kernel-style barriers. It was just
the rationale that seemed flawed to me.
If Linux kernel-style memory barriers took a memory model parameter, we
would still prefer C11-style GCC barrier intrinsics (for this release).
>>
>> The old <rte_atomic.h> atomic arithmetic and atomic load/store operations suffered from
>> unspecified semantics in regards to any ordering they imposed on other memory accesses. I
>> guess that shortcoming could be described as a "missing parameter", although that too
>> would be misleading. Unclear semantics seems not be the case for the kernel-style barriers
>> though.
>>
>>> */
>>> static inline void rte_smp_mb(void);
>>>
>>> @@ -64,6 +69,11 @@ static inline void rte_smp_mb(void);
>>> * Guarantees that the STORE operations that precede the
>>> * rte_smp_wmb() call are globally visible across the lcores
>>> * before the STORE operations that follows it.
>>> + *
>>> + * @note
>>> + * This function is deprecated. It provides fence synchronization
>>> + * primitive but doesn't take memory order parameter.
>>> + * rte_atomic_thread_fence() should be used instead.
>>> */
>>> static inline void rte_smp_wmb(void);
>>>
>>> @@ -73,6 +83,11 @@ static inline void rte_smp_wmb(void);
>>> * Guarantees that the LOAD operations that precede the
>>> * rte_smp_rmb() call are globally visible across the lcores
>>> * before the LOAD operations that follows it.
>>> + *
>>> + * @note
>>> + * This function is deprecated. It provides fence synchronization
>>> + * primitive but doesn't take memory order parameter.
>>> + * rte_atomic_thread_fence() should be used instead.
>>> */
>>> static inline void rte_smp_rmb(void);
>>> ///@}
>>> @@ -122,6 +137,10 @@ static inline void rte_io_rmb(void);
>>>
>>> /**
>>> * Synchronization fence between threads based on the specified memory order.
>>> + *
>>> + * @param memorder
>>> + * The memory order defined by compiler atomic builtin at:
>>> + * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
>>> */
>>> static inline void rte_atomic_thread_fence(int memorder);
>>>
@@ -55,6 +55,11 @@ static inline void rte_rmb(void);
* Guarantees that the LOAD and STORE operations that precede the
* rte_smp_mb() call are globally visible across the lcores
* before the LOAD and STORE operations that follows it.
+ *
+ * @note
+ * This function is deprecated. It provides fence synchronization
+ * primitive but doesn't take memory order parameter.
+ * rte_atomic_thread_fence() should be used instead.
*/
static inline void rte_smp_mb(void);
@@ -64,6 +69,11 @@ static inline void rte_smp_mb(void);
* Guarantees that the STORE operations that precede the
* rte_smp_wmb() call are globally visible across the lcores
* before the STORE operations that follows it.
+ *
+ * @note
+ * This function is deprecated. It provides fence synchronization
+ * primitive but doesn't take memory order parameter.
+ * rte_atomic_thread_fence() should be used instead.
*/
static inline void rte_smp_wmb(void);
@@ -73,6 +83,11 @@ static inline void rte_smp_wmb(void);
* Guarantees that the LOAD operations that precede the
* rte_smp_rmb() call are globally visible across the lcores
* before the LOAD operations that follows it.
+ *
+ * @note
+ * This function is deprecated. It provides fence synchronization
+ * primitive but doesn't take memory order parameter.
+ * rte_atomic_thread_fence() should be used instead.
*/
static inline void rte_smp_rmb(void);
///@}
@@ -122,6 +137,10 @@ static inline void rte_io_rmb(void);
/**
* Synchronization fence between threads based on the specified memory order.
+ *
+ * @param memorder
+ * The memory order defined by compiler atomic builtin at:
+ * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
*/
static inline void rte_atomic_thread_fence(int memorder);