diff mbox series

[v2,10/17] net/ice: add checks for max SIMD bitwidth

Message ID	20200827161304.32300-11-ciara.power@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	David Marchand
Headers	IronPort-SDR: 64tDxak4JnvRc1T2+C1ElJk1nS2Yx+hNRLI6vxgjq/Y/sdquyQZRR6RWtxlO6+CZJN7GZ8Qite Sop2S9XMO4DQ== IronPort-SDR: xdJL+DWlxWKXeO8z0Mnsz0DMJj0d27brkpfLocA5L7FdMgXRsyPkQ6V/HHbPiGFYX1L6bq3Hf+ z3oBgcajoB2w== From: Ciara Power <ciara.power@intel.com> To: dev@dpdk.org Cc: Ciara Power <ciara.power@intel.com>, Qiming Yang <qiming.yang@intel.com>, Qi Zhang <qi.z.zhang@intel.com> Date: Thu, 27 Aug 2020 17:12:57 +0100 Message-Id: <20200827161304.32300-11-ciara.power@intel.com> In-Reply-To: <20200827161304.32300-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200827161304.32300-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v2 10/17] net/ice: add checks for max SIMD bitwidth Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	add max SIMD bitwidth to EAL \| [v2,00/17] add max SIMD bitwidth to EAL [v2,01/17] eal: add max SIMD bitwidth [v2,02/17] eal: add default SIMD bitwidth values [v2,03/17] doc: add detail on using max SIMD bitwidth [v2,04/17] net/i40e: add checks for max SIMD bitwidth [v2,05/17] net/axgbe: add checks for max SIMD bitwidth [v2,06/17] net/bnxt: add checks for max SIMD bitwidth [v2,07/17] net/enic: add checks for max SIMD bitwidth [v2,08/17] net/fm10k: add checks for max SIMD bitwidth [v2,09/17] net/iavf: add checks for max SIMD bitwidth [v2,10/17] net/ice: add checks for max SIMD bitwidth [v2,11/17] net/ixgbe: add checks for max SIMD bitwidth [v2,12/17] net/mlx5: add checks for max SIMD bitwidth [v2,13/17] net/virtio: add checks for max SIMD bitwidth [v2,14/17] distributor: add checks for max SIMD bitwidth [v2,15/17] member: add checks for max SIMD bitwidth [v2,16/17] efd: add checks for max SIMD bitwidth [v2,17/17] net: add checks for max SIMD bitwidth

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Power, Ciara Aug. 27, 2020, 4:12 p.m. UTC

  When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Cc: Qiming Yang <qiming.yang@intel.com>
Cc: Qi Zhang <qi.z.zhang@intel.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
---
 drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff mbox series

Patch

diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c
index 2e1f06d2c0..eda2d9a8c7 100644
--- a/drivers/net/ice/ice_rxtx.c
+++ b/drivers/net/ice/ice_rxtx.c
@@ -2889,7 +2889,9 @@  ice_set_rx_function(struct rte_eth_dev *dev)
 	bool use_avx2 = false;
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
-		if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
+		if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed &&
+				rte_get_max_simd_bitwidth()
+				>= RTE_MAX_128_SIMD) {
 			ad->rx_vec_allowed = true;
 			for (i = 0; i < dev->data->nb_rx_queues; i++) {
 				rxq = dev->data->rx_queues[i];
@@ -2899,8 +2901,10 @@  ice_set_rx_function(struct rte_eth_dev *dev)
 				}
 			}
 
-			if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
+			if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
+					rte_get_max_simd_bitwidth()
+					>= RTE_MAX_256_SIMD)
 				use_avx2 = true;
 
 		} else {
@@ -3067,7 +3071,9 @@  ice_set_tx_function(struct rte_eth_dev *dev)
 	bool use_avx2 = false;
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
-		if (!ice_tx_vec_dev_check(dev)) {
+		if (!ice_tx_vec_dev_check(dev) &&
+				rte_get_max_simd_bitwidth()
+				>= RTE_MAX_128_SIMD) {
 			ad->tx_vec_allowed = true;
 			for (i = 0; i < dev->data->nb_tx_queues; i++) {
 				txq = dev->data->tx_queues[i];
@@ -3077,8 +3083,10 @@  ice_set_tx_function(struct rte_eth_dev *dev)
 				}
 			}
 
-			if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
+			if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
+					rte_get_max_simd_bitwidth()
+					>= RTE_MAX_256_SIMD)
 				use_avx2 = true;
 
 		} else {