From patchwork Wed May 11 12:30:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 111027 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 78A87A0032; Wed, 11 May 2022 14:31:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B23940DDD; Wed, 11 May 2022 14:31:03 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id F0A23406B4 for ; Wed, 11 May 2022 14:31:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652272261; x=1683808261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YlVWevYv+aP2hwals/hSUAik3848akaSaHK4m5SYUS0=; b=ZYmsftnKCCIl3m9AKb+4MxJSmivunQJVnXUAFcH4NdxtvseDQVsjkVU/ muBx1vvXT53gQfPHGEjjxq0YEYHEx6B5eUDn1EPMOkrlMaIupHJw8WoIK ZWezp9eY9zbZjSy63jKIW4CWFztk6cU2Jt6p/BVCTJFRCFRvbm1BbJeBX xhlVYuDmOVoLO1dzo0UmuJxQ6CMqWYDocAkKIUnzBmVorbkWe8wRcIjE3 WkjSuY/Z+jKkj9Dlk/2F6svMgOEOyx/dR7QJ1IF5bUon8vGDoXyxlsQAR ajmLmBCXv8AJJxqV/YF6wN2hVmkpuICQ6N+cHrZatYU1dnfbgYSxcKDCU w==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="294922348" X-IronPort-AV: E=Sophos;i="5.91,217,1647327600"; d="scan'208";a="294922348" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 05:30:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,217,1647327600"; d="scan'208";a="566157913" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.49]) by orsmga007.jf.intel.com with ESMTP; 11 May 2022 05:30:58 -0700 From: Ciara Power To: dev@dpdk.org Cc: roy.fan.zhang@intel.com, kai.ji@intel.com, pablo.de.lara.guarch@intel.com, Ciara Power Subject: [PATCH v2 0/2] add partial SGL support to AESNI_MB Date: Wed, 11 May 2022 12:30:43 +0000 Message-Id: <20220511123045.1154799-1-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220407103041.4037942-1-ciara.power@intel.com> References: <20220407103041.4037942-1-ciara.power@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patchset adds SGL support for GCM and CHACHA20-POLY1305 algorithms, using the IPSec-MB JOB API. Supported SGL types: - INPLACE SGL - OOP SGL IN, LB OUT - OOP SGL IN, SGL OUT The SGL Feature Flags for AESNI_MB PMD are not added, as it does not yet support SGL for all other algorithms. --- v2: - Moved GCM and CHACHAPOLY context from session to qp_data. - Removed redundant if condition checks. - Added setting job SGL state to IMB_SGL_INIT for the first job. - Squashed third patch into other patches. Ciara Power (2): crypto/ipsec_mb: add GCM SGL support to aesni-mb crypto/ipsec_mb: add chachapoly SGL support to aesni-mb drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 162 +++++++++++++++++++- drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 4 + 2 files changed, 161 insertions(+), 5 deletions(-)