| Message ID | 20230519083110.809913-1-wenjing.qiao@intel.com (mailing list archive) |
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| Headers |
Return-Path: <dev-bounces@dpdk.org> X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D44B42B47; Fri, 19 May 2023 10:36:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DE35A41148; Fri, 19 May 2023 10:36:20 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 78CCA40F16 for <dev@dpdk.org>; Fri, 19 May 2023 10:36:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684485378; x=1716021378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+2aTEjQjsof01uIkI5SwbyA7q0YWr8zmLeTRv3nO7L0=; b=gwk2bf+LWK0o7KkQ1Ck/AiGHgHGKgAtpa4T1LQiSCA33306hus55PRU+ OyD2EgpdhfIERyELF5h3B2gbdcuQ5rRnQNUaTrDIJwEdl7su9d0UkF5bC HlqzxliwBFF6YirHQjIGY/vfrzTjDfgMV0fGDtm51VpJRAJ1tNk4uUvPl 8fq9mIqDkeL7DshDlAyx+3DIKnxydc6+RlRywCOqU+ScjA2PaVAU1AVCx 3SWD9XcauVnwJI0LwwxgdW41+u6yfFehJGgwwj13S1rpAwf8gMD5JK4wy zU5ew8KjaIOooMLXlU8mQ1xCHiGZBp3Qqyc/CVPbjDEK9PmP7ADc7ykbT A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="354670219" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="354670219" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2023 01:36:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="772215818" X-IronPort-AV: E=Sophos;i="6.00,176,1681196400"; d="scan'208";a="772215818" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.161]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2023 01:36:14 -0700 From: Wenjing Qiao <wenjing.qiao@intel.com> To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao <wenjing.qiao@intel.com> Subject: [PATCH v4 0/7] fix idpf and cpfl timestamp Date: Fri, 19 May 2023 04:31:03 -0400 Message-Id: <20230519083110.809913-1-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-2-wenjing.qiao@intel.com> References: <20230424091707.488045-2-wenjing.qiao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org |
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fix idpf and cpfl timestamp
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Message
Wenjing Qiao
May 19, 2023, 8:31 a.m. UTC
Using alarm to save main time to solve timestamp roll over issue. Enhance timestamp offload feature support for ACC. Ajust timestamp mbuf register to dev config. *** BLURB HERE *** Wenjing Qiao (7): common/idpf: fix 64b timestamp roll over issue net/idpf: save main time by alarm net/cpfl: save main time by alarm common/idpf: enhance timestamp offload feature for ACC common/idpf: add timestamp enable flag for rxq net/cpfl: adjust timestamp mbuf register net/idpf: adjust timestamp mbuf register drivers/common/idpf/base/idpf_osdep.h | 48 ++++++++ drivers/common/idpf/idpf_common_rxtx.c | 159 ++++++++++++++++--------- drivers/common/idpf/idpf_common_rxtx.h | 8 +- drivers/common/idpf/meson.build | 2 + drivers/common/idpf/version.map | 2 + drivers/net/cpfl/cpfl_ethdev.c | 12 ++ drivers/net/cpfl/cpfl_rxtx.c | 2 + drivers/net/idpf/idpf_ethdev.c | 12 ++ drivers/net/idpf/idpf_rxtx.c | 3 + 9 files changed, 190 insertions(+), 58 deletions(-)