From patchwork Mon Jan 8 20:21:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 544 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB43243864; Mon, 8 Jan 2024 12:54:25 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 40964402EF; Mon, 8 Jan 2024 12:54:25 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mails.dpdk.org (Postfix) with ESMTP id 3A42440261 for ; Mon, 8 Jan 2024 12:54:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704714864; x=1736250864; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=asSAFxkE8YWVQWk2WRdJhIxM/5D40kfyvlOU/i1tF30=; b=FptHj6HBZxPAAmwGDgo3A40uXS6nN9aF8CCPuYhUamvnoY0MmKBIDtd5 4T2ZmqRDNdSh18p3VtJlgYVzRLzlxKRgUafLSHOcHmItAX4WTHhSHI4Kk kPPVPc4LBBAksVTBm7NvqK2xE5KKZIPkPSdH2Bc5yiCCNf4vDd5MDauuj vzp58tylR/fUFUZqF3jJCKugAaGPkzBR5xJPIX7SA0jgEmKxWz+FS6sVZ FLGqYgDG+xvaJ8B2NhNZJ/cKyzN0/g5psq2Ls1ZVQ6pFZSJPDoxQaV05r eNAOAp4+oYDzNewW+ET7X+RhSfcXThOsk3CsIk3/VaXbHUt7JmsiZeahG g==; X-IronPort-AV: E=McAfee;i="6600,9927,10946"; a="4650106" X-IronPort-AV: E=Sophos;i="6.04,341,1695711600"; d="scan'208";a="4650106" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2024 03:54:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10946"; a="851784647" X-IronPort-AV: E=Sophos;i="6.04,341,1695711600"; d="scan'208";a="851784647" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.119.16]) by fmsmga004.fm.intel.com with ESMTP; 08 Jan 2024 03:54:21 -0800 From: Qi Zhang To: qiming.yang@intel.com, wenjun1.wu@intel.com Cc: dev@dpdk.org, Qi Zhang Subject: [PATCH v4 0/3] simplified to 3 layer Tx scheduler Date: Mon, 8 Jan 2024 15:21:55 -0500 Message-Id: <20240108202158.567910-1-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240105211237.394105-1-qi.z.zhang@intel.com> References: <20240105211237.394105-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove dummy layers, code refactor, complete document v4: - rebase. v3: - fix tm_node memory free. - fix corrupt when slibling node deletion is not in a reversed order. v2: - fix typos. Qi Zhang (3): net/ice: hide port and TC layer in Tx sched tree net/ice: refactor tm config data structure doc: update ice document for qos doc/guides/nics/ice.rst | 19 +++ drivers/net/ice/ice_ethdev.h | 12 +- drivers/net/ice/ice_tm.c | 317 +++++++++++++---------------------- 3 files changed, 134 insertions(+), 214 deletions(-)