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[dpdk-dev,v3,3/5] ixgbe: Config PFVML2FLT register

Message ID 1414732757-7241-4-git-send-email-changchun.ouyang@intel.com (mailing list archive)
State Superseded, archived
Headers

Commit Message

Ouyang Changchun Oct. 31, 2014, 5:19 a.m. UTC 
Config PFVML2FLT register in ixgbe PMD to enable it 
receive broadcast and multicast packets.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
---
 lib/librte_pmd_ixgbe/ixgbe_rxtx.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Thomas Monjalon Nov. 6, 2014, 1:57 p.m. UTC | #1 
Title would be more high level.
Example: "ixgbe: configure Rx mode for VMDQ"

2014-10-31 13:19, Ouyang Changchun:
> +	for (i = 0; i < (int)num_pools; i++) {
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
> +			vmolr |= IXGBE_VMOLR_AUPE;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
> +			vmolr |= IXGBE_VMOLR_ROMPE;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
> +			vmolr |= IXGBE_VMOLR_ROPE;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
> +			vmolr |= IXGBE_VMOLR_BAM;
> +		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
> +			vmolr |= IXGBE_VMOLR_MPE;
> +
> +		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
> +	}

Please factorize code with ixgbe_set_pool_rx_mode() which is really similar.
diff mbox

Patch

diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
index 3a5a8ff..96276a7 100644
--- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
+++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
@@ -3123,6 +3123,7 @@  ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
 	struct ixgbe_hw *hw;
 	enum rte_eth_nb_pools num_pools;
 	uint32_t mrqc, vt_ctl, vlanctrl;
+	uint32_t vmolr = 0;
 	int i;
 
 	PMD_INIT_FUNC_TRACE();
@@ -3145,6 +3146,21 @@  ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
 
 	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
 
+	for (i = 0; i < (int)num_pools; i++) {
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
+			vmolr |= IXGBE_VMOLR_AUPE;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
+			vmolr |= IXGBE_VMOLR_ROMPE;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
+			vmolr |= IXGBE_VMOLR_ROPE;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
+			vmolr |= IXGBE_VMOLR_BAM;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
+			vmolr |= IXGBE_VMOLR_MPE;
+
+		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
+	}
+
 	/* VLNCTRL: enable vlan filtering and allow all vlan tags through */
 	vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 	vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */