From patchwork Fri Jan 15 02:40:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Helin" X-Patchwork-Id: 9887 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id AF7AE9212; Fri, 15 Jan 2016 03:41:45 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 2A79F91B8 for ; Fri, 15 Jan 2016 03:41:43 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP; 14 Jan 2016 18:41:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,297,1449561600"; d="scan'208";a="633696633" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 14 Jan 2016 18:41:43 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u0F2fdPv003445; Fri, 15 Jan 2016 10:41:39 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u0F2faBR000793; Fri, 15 Jan 2016 10:41:38 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u0F2fZGi000789; Fri, 15 Jan 2016 10:41:36 +0800 From: Helin Zhang To: dev@dpdk.org Date: Fri, 15 Jan 2016 10:40:43 +0800 Message-Id: <1452825653-623-20-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1452825653-623-1-git-send-email-helin.zhang@intel.com> References: <1452825653-623-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH 19/29] i40e/base: Increase timeout when checking GLGEN_RSTAT_DEVSTATE bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When linking with particular PHY types (ex: copper PHY), the amount of time it takes for the GLGEN_RSTAT_DEVSTATE to be set increases greatly, which can lead to a timeout and failure to load the driver. Signed-off-by: Helin Zhang --- drivers/net/i40e/base/i40e_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index a4cf5cf..925bb1c 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -1316,11 +1316,11 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; -#ifdef I40E_ESS_SUPPORT + /* It can take upto 15 secs for GRST steady state */ grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */ -#endif - for (cnt = 0; cnt < grst_del + 10; cnt++) { + + for (cnt = 0; cnt < grst_del; cnt++) { reg = rd32(hw, I40E_GLGEN_RSTAT); if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) break;