From patchwork Fri Mar 4 18:08:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Hemminger X-Patchwork-Id: 11077 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id B93C92BE6; Fri, 4 Mar 2016 19:08:00 +0100 (CET) Received: from mail-pa0-f48.google.com (mail-pa0-f48.google.com [209.85.220.48]) by dpdk.org (Postfix) with ESMTP id E4C432BE4 for ; Fri, 4 Mar 2016 19:07:58 +0100 (CET) Received: by mail-pa0-f48.google.com with SMTP id bj10so38859664pad.2 for ; Fri, 04 Mar 2016 10:07:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MpVpbMVahOem2mi6VtwrzsLPbPn59AaFG37zpy1cKWk=; b=rnscEhGe7duDBXAAJ08wsah0jbg82hVsYijrYg9/GS2Eb1Ii38FTmGyekxFsYX3sgE Nu7ewYX5rouN+00TVWfR6AEhTnWekiTaX8orpy636x27PZi0i+5Beg0olP8M4KnsPkut pp/xT1t1IBcHS4M63eyy81iIPF8WMWikRbJBAM4gu65MUs+RjatU/9j65fgfWSyOhfHe IRaFb2xbnQAeH7fLQamHpZ10oEV0TPGcG9RrdHMFSSU/I47dreTS8cl0q4I32Z6ZanMf BfxIP8fwm9r8KwXSXWdeM2bzTDuownW7IwyDECCctbBUjuG6sg5lEKXYjLIJht0fSDgL NSJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MpVpbMVahOem2mi6VtwrzsLPbPn59AaFG37zpy1cKWk=; b=Zzph5l+8GOR3zWm2DoYML2TA9UF0B5ZYnuFNn2iFNG/krFjbvi31JEb7dGaiocLcib a7kaSMWMEbZ+4BB+UkqWRNwsi82a+nPn2DhpQOZIXoFsdlylpziYCkdQwff68BHXOO+K XWeJRRhCcRTgLhH88LrIZVZVweasa7JEYBP9VLzDiqXJB9/CO1sdKwYR0oaiAgvKJtYs f1cnI5ymF3FZ6tKUzVEjn/IxQgohCWRlrxtJvHAafqj3oQSabBtpjP4cIFveEgDpKw+I QwVJZPOz6IcVDV78uETZPk1n7FtW/dwIx+sD6Vh88Fm63MNjcChEUDNyA4EIetJlPIvW gLVA== X-Gm-Message-State: AD7BkJIOlGbLjTrbGo2Ug5CRo0+iTLZlson741/xlL91fXOYjmmWKs8eBfyx/bCbEeQQzg== X-Received: by 10.66.253.169 with SMTP id ab9mr14251474pad.62.1457114877684; Fri, 04 Mar 2016 10:07:57 -0800 (PST) Received: from xeon-e3.home.lan (static-50-53-82-155.bvtn.or.frontiernet.net. [50.53.82.155]) by smtp.gmail.com with ESMTPSA id f8sm7014701pfj.49.2016.03.04.10.07.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Mar 2016 10:07:56 -0800 (PST) From: Stephen Hemminger To: dev@dpdk.org Date: Fri, 4 Mar 2016 10:08:01 -0800 Message-Id: <1457114882-22125-3-git-send-email-stephen@networkplumber.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1457114882-22125-1-git-send-email-stephen@networkplumber.org> References: <1457114882-22125-1-git-send-email-stephen@networkplumber.org> Cc: "Charles \(Chas\) Williams" , Nachiketa Prachanda Subject: [dpdk-dev] [PATCH 2/3] vmxnet3: Fix VLAN filtering X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Charles (Chas) Williams" During an MTU change, the adapter is restarted. If hardware VLAN offload is in use, this existing filter table would also be cleared. Instead, setup the shadow table once during device initialization and just update during restart. vmxnet3_dev_vlan_offload_set(dev, mask) was incorrectly treating the mask parameter as the bitmask for vlan_strip and vlan_filter, whereas the mask indicates only what has changed - the values for vlan_stripping and vlan_filter needs to be taken from dev_conf.rxmode. Signed-off-by: "Charles (Chas) Williams" Signed-off-by: Nachiketa Prachanda Signed-off-by: Stephen Hemminger --- drivers/net/vmxnet3/vmxnet3_ethdev.c | 62 +++++++++++++----------------------- 1 file changed, 22 insertions(+), 40 deletions(-) diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c index 585ee60..111ec8e 100644 --- a/drivers/net/vmxnet3/vmxnet3_ethdev.c +++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c @@ -89,8 +89,6 @@ static void vmxnet3_dev_info_get(struct rte_eth_dev *dev, static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask); -static void vmxnet3_dev_vlan_offload_set_clear(struct rte_eth_dev *dev, - int mask, int clear); #if PROCESS_SYS_EVENTS == 1 static void vmxnet3_process_events(struct vmxnet3_hw *); @@ -294,6 +292,9 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev) /* Put device in Quiesce Mode */ VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV); + /* allow untagged pkts */ + VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); + return 0; } @@ -430,7 +431,7 @@ vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) Vmxnet3_DSDevRead *devRead = &shared->devRead; uint32_t *mac_ptr; uint32_t val, i; - int ret, mask; + int ret; shared->magic = VMXNET3_REV1_MAGIC; devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM; @@ -512,14 +513,8 @@ vmxnet3_setup_driver_shared(struct rte_eth_dev *dev) devRead->rssConfDesc.confPA = hw->rss_confPA; } - mask = 0; - if (dev->data->dev_conf.rxmode.hw_vlan_strip) - mask |= ETH_VLAN_STRIP_MASK; - - if (dev->data->dev_conf.rxmode.hw_vlan_filter) - mask |= ETH_VLAN_FILTER_MASK; - - vmxnet3_dev_vlan_offload_set_clear(dev, mask, 1); + vmxnet3_dev_vlan_offload_set(dev, + ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); PMD_INIT_LOG(DEBUG, "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x", @@ -836,44 +831,31 @@ vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) } static void -vmxnet3_dev_vlan_offload_set_clear(struct rte_eth_dev *dev, - int mask, int clear) +vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) { struct vmxnet3_hw *hw = dev->data->dev_private; Vmxnet3_DSDevRead *devRead = &hw->shared->devRead; uint32_t *vf_table = devRead->rxFilterConf.vfTable; - if (mask & ETH_VLAN_STRIP_MASK) - devRead->misc.uptFeatures |= UPT1_F_RXVLAN; - else - devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; + if (mask & ETH_VLAN_STRIP_MASK) { + if (dev->data->dev_conf.rxmode.hw_vlan_strip) + devRead->misc.uptFeatures |= UPT1_F_RXVLAN; + else + devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN; - VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, - VMXNET3_CMD_UPDATE_FEATURE); - - if (mask & ETH_VLAN_FILTER_MASK) { - if (clear) { - memset(hw->shadow_vfta, 0, - VMXNET3_VFT_TABLE_SIZE); - /* allow untagged pkts */ - VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0); - } - memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); - } else { - /* allow any pkts -- no filtering */ - if (clear) - memset(hw->shadow_vfta, 0xff, VMXNET3_VFT_TABLE_SIZE); - memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, + VMXNET3_CMD_UPDATE_FEATURE); } - VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, - VMXNET3_CMD_UPDATE_VLAN_FILTERS); -} + if (mask & ETH_VLAN_FILTER_MASK) { + if (dev->data->dev_conf.rxmode.hw_vlan_filter) + memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE); + else + memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE); -static void -vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask) -{ - vmxnet3_dev_vlan_offload_set_clear(dev, mask, 0); + VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, + VMXNET3_CMD_UPDATE_VLAN_FILTERS); + } } #if PROCESS_SYS_EVENTS == 1