From patchwork Fri May 6 06:07:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xing, Beilei" X-Patchwork-Id: 12436 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id D31DE5A92; Fri, 6 May 2016 08:08:22 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 715865A92 for ; Fri, 6 May 2016 08:08:21 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 05 May 2016 23:08:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,585,1455004800"; d="scan'208";a="697627319" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 05 May 2016 23:08:21 -0700 Received: from shecgisg003.sh.intel.com (shecgisg003.sh.intel.com [10.239.29.90]) by shvmail01.sh.intel.com with ESMTP id u4668I0t015604; Fri, 6 May 2016 14:08:18 +0800 Received: from shecgisg003.sh.intel.com (localhost [127.0.0.1]) by shecgisg003.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u4668GG2029544; Fri, 6 May 2016 14:08:18 +0800 Received: (from beileixi@localhost) by shecgisg003.sh.intel.com (8.13.6/8.13.6/Submit) id u4668FuG029540; Fri, 6 May 2016 14:08:15 +0800 From: Beilei Xing To: helin.zhang@intel.com Cc: dev@dpdk.org, Beilei Xing Date: Fri, 6 May 2016 14:07:25 +0800 Message-Id: <1462514861-29419-14-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1462514861-29419-1-git-send-email-beilei.xing@intel.com> References: <1462514861-29419-1-git-send-email-beilei.xing@intel.com> Subject: [dpdk-dev] [PATCH 13/29] ixgbe/base: refactor NW management interface ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds ixgbe_read_mng_if_sel_x550em to read NW_MNG_IF_SEL register and save fields such as PHY MDIO_ADD. Signed-off-by: Beilei Xing --- drivers/net/ixgbe/base/ixgbe_type.h | 2 ++ drivers/net/ixgbe/base/ixgbe_x550.c | 48 +++++++++++++++++++++++-------------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index de295e1..da1fe16 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -4134,6 +4134,8 @@ struct ixgbe_hw { #define IXGBE_SB_IOSF_TARGET_KR_PHY 0 #define IXGBE_NW_MNG_IF_SEL 0x00011178 +#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1 << 1) +#define IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M (1 << 23) #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \ diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index e91546c..22081d4 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -338,9 +338,8 @@ static s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw) { u16 phy_id_high; u16 phy_id_low; - u32 val = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); + u32 val; - hw->phy.addr = (val >> 3) & 0x1F; val = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, hw->phy.addr, &phy_id_high); if (val || phy_id_high == 0xFFFF) { @@ -1842,6 +1841,33 @@ STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, } /** + * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register + * @hw: pointer to hardware structure + * + * Read NW_MNG_IF_SEL register and save field values, and check for valid field + * values. + **/ +STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) +{ + /* Save NW management interface connected on board. This is used + * to determine internal PHY mode. + */ + hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); + + /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set + * PHY address. This register field was has only been used for X552. + */ + if (hw->mac.type == ixgbe_mac_X550EM_a && + hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { + hw->phy.addr = (hw->phy.nw_mng_if_sel & + IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> + IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; + } + + return IXGBE_SUCCESS; +} + +/** * ixgbe_init_phy_ops_X550em - PHY/SFP specific init * @hw: pointer to hardware structure * @@ -1858,14 +1884,11 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) hw->mac.ops.set_lan_id(hw); + ixgbe_read_mng_if_sel_x550em(hw); + if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; ixgbe_setup_mux_ctl(hw); - - /* Save NW management interface connected on board. This is used - * to determine internal PHY mode. - */ - phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; } @@ -1892,11 +1915,6 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) phy->ops.write_reg = ixgbe_write_phy_reg_x550em; break; case ixgbe_phy_x550em_ext_t: - /* Save NW management interface connected on board. This is used - * to determine internal PHY mode - */ - phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); - /* If internal link mode is XFI, then setup iXFI internal link, * else setup KR now. */ @@ -2255,12 +2273,6 @@ s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, /* Configure internal PHY for KR/KX. */ ixgbe_setup_kr_speed_x550em(hw, speed); - /* Get CS4227 MDIO address */ - hw->phy.addr = - (hw->phy.nw_mng_if_sel & - IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) - >> IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; - if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) { /* Find Address */ DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");