From patchwork Thu Mar 23 10:57:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xing, Beilei" X-Patchwork-Id: 22159 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 7CDA1CFA8; Thu, 23 Mar 2017 11:59:16 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id EA60169EC for ; Thu, 23 Mar 2017 11:58:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490266737; x=1521802737; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=cCGSLK1YpEtO/SBbiIvPV6ibqifVriWTLH72NoGMY8c=; b=O0sxxOojB61+GbX6M7M9frc9SmoYye3pufI5GuuHsrfOsjUejGFBUESR a/Jc/sMvCckIV7KPsU+Hu8BF9Kr4Wg==; Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Mar 2017 03:58:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,209,1486454400"; d="scan'208"; a="1126152722" Received: from unknown (HELO dpdk9.sh.intel.com) ([10.239.129.31]) by fmsmga001.fm.intel.com with ESMTP; 23 Mar 2017 03:58:55 -0700 From: Beilei Xing To: jingjing.wu@intel.com Cc: helin.zhang@intel.com, dev@dpdk.org Date: Thu, 23 Mar 2017 18:57:49 +0800 Message-Id: <1490266669-122137-4-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1490266669-122137-1-git-send-email-beilei.xing@intel.com> References: <1488534236-29904-1-git-send-email-beilei.xing@intel.com> <1490266669-122137-1-git-send-email-beilei.xing@intel.com> Subject: [dpdk-dev] [PATCH v2 3/3] net/i40e: enable tunnel filter for MPLS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch enables MPLS tunnel filter by replacing inner_mac filter. This configuration will be set when adding MPLSoUDP and MPLSoGRE filter rules, and it will be invalid only by NIC core reset. Signed-off-by: Beilei Xing --- drivers/net/i40e/i40e_ethdev.c | 45 +++++++++++++++-- drivers/net/i40e/i40e_ethdev.h | 11 ++++- drivers/net/i40e/i40e_flow.c | 110 +++++++++++++++++++++++++++++++++++++---- 3 files changed, 149 insertions(+), 17 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 506b957..5e6e2f5 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -6954,6 +6954,7 @@ i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel; struct i40e_tunnel_filter *tunnel, *node; struct i40e_tunnel_filter check_filter; /* Check if filter exists */ + uint32_t teid_le; bool big_buffer = 0; cld_filter = rte_zmalloc("tunnel_filter", @@ -7002,6 +7003,32 @@ i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, case I40E_TUNNEL_TYPE_IP_IN_GRE: tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; break; + case I40E_TUNNEL_TYPE_MPLSoUDP: + i40e_replace_mpls_l1_filter(pf); + i40e_replace_mpls_cloud_filter(pf); + teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); + pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = + teid_le >> 4; + pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = + (teid_le & 0xF) << 12; + pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = + 0x40; + big_buffer = 1; + tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP; + break; + case I40E_TUNNEL_TYPE_MPLSoGRE: + i40e_replace_mpls_l1_filter(pf); + i40e_replace_mpls_cloud_filter(pf); + teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id); + pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] = + teid_le >> 4; + pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] = + (teid_le & 0xF) << 12; + pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] = + 0x0; + big_buffer = 1; + tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE; + break; default: /* Other tunnel types is not supported. */ PMD_DRV_LOG(ERR, "tunnel type is not supported."); @@ -7009,11 +7036,19 @@ i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, return -EINVAL; } - val = i40e_dev_get_filter_type(tunnel_filter->filter_type, - &pfilter->element.flags); - if (val < 0) { - rte_free(cld_filter); - return -EINVAL; + if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP) + pfilter->element.flags = + I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP; + else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE) + pfilter->element.flags = + I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE; + else { + val = i40e_dev_get_filter_type(tunnel_filter->filter_type, + &pfilter->element.flags); + if (val < 0) { + rte_free(cld_filter); + return -EINVAL; + } } pfilter->element.flags |= rte_cpu_to_le_16( diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index df345b1..934c679 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -500,8 +500,13 @@ struct i40e_ethertype_rule { /* Tunnel filter number HW supports */ #define I40E_MAX_TUNNEL_FILTER_NUM 400 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP 0x11 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE 0x12 +#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44 +#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45 +#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP 8 +#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE 9 +#define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP 0x11 +#define I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE 0x12 +#define I40E_AQC_ADD_L1_FILTER_TEID_MPLS 0x11 enum i40e_tunnel_iptype { I40E_TUNNEL_IPTYPE_IPV4, @@ -863,6 +868,8 @@ int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, struct i40e_tunnel_filter_conf *tunnel_filter, uint8_t add); int i40e_fdir_flush(struct rte_eth_dev *dev); +enum i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf); +enum i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf); #define I40E_DEV_TO_PCI(eth_dev) \ RTE_DEV_TO_PCI((eth_dev)->device) diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index eefb15b..8d7765a 100644 --- a/drivers/net/i40e/i40e_flow.c +++ b/drivers/net/i40e/i40e_flow.c @@ -1953,16 +1953,10 @@ i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf, filter->input.general_fields, sizeof(cld_filter.general_fields)); - if (((filter->input.flags & - (I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP << - I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)) == - (I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP << - I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)) || - ((filter->input.flags & - (I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE << - I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT)) == - (I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE << - I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT))) + if ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) == + I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP || + (filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) == + I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) big_buffer = 1; if (big_buffer) @@ -2103,3 +2097,99 @@ i40e_flow_flush_tunnel_filter(struct i40e_pf *pf) return ret; } + +enum +i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) +{ + struct i40e_aqc_replace_cloud_filters_cmd filter_replace; + struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; + struct i40e_hw *hw = I40E_PF_TO_HW(pf); + enum i40e_status_code status = I40E_SUCCESS; + + memset(&filter_replace, 0, + sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); + memset(&filter_replace_buf, 0, + sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); + + /* create L1 filter */ + filter_replace.old_filter_type = + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC; + filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS; + filter_replace.tr_bit = 0xFF; + + /* Prepare the buffer, 3 entries */ + filter_replace_buf.data[0] = + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0; + filter_replace_buf.data[0] |= + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; + filter_replace_buf.data[2] = 0xff; + filter_replace_buf.data[3] = 0xff; + filter_replace_buf.data[4] = + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1; + filter_replace_buf.data[4] |= + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; + filter_replace_buf.data[7] = 0xf0; + filter_replace_buf.data[8] = 0x48; + filter_replace_buf.data[8] |= + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; + filter_replace_buf.data[10] = 0x4c; + filter_replace_buf.data[11] = 0x8c; + + status = i40e_aq_replace_cloud_filters(hw, &filter_replace, + &filter_replace_buf); + return status; +} + +enum +i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) +{ + struct i40e_aqc_replace_cloud_filters_cmd filter_replace; + struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf; + struct i40e_hw *hw = I40E_PF_TO_HW(pf); + enum i40e_status_code status = I40E_SUCCESS; + + /* For MPLSoUDP */ + memset(&filter_replace, 0, + sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); + memset(&filter_replace_buf, 0, + sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); + filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | + I40E_AQC_MIRROR_CLOUD_FILTER; + filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP; + filter_replace.new_filter_type = + I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP; + /* Prepare the buffer, 2 entries */ + filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; + filter_replace_buf.data[0] |= + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; + filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS; + filter_replace_buf.data[4] |= + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; + status = i40e_aq_replace_cloud_filters(hw, &filter_replace, + &filter_replace_buf); + if (status < 0) + return status; + + /* For MPLSoGRE */ + memset(&filter_replace, 0, + sizeof(struct i40e_aqc_replace_cloud_filters_cmd)); + memset(&filter_replace_buf, 0, + sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf)); + + filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER | + I40E_AQC_MIRROR_CLOUD_FILTER; + filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC; + filter_replace.new_filter_type = + I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE; + /* Prepare the buffer, 2 entries */ + filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG; + filter_replace_buf.data[0] |= + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; + filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS; + filter_replace_buf.data[4] |= + I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; + + status = i40e_aq_replace_cloud_filters(hw, &filter_replace, + &filter_replace_buf); + return status; +}