From patchwork Mon Jun 5 21:14:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 25060 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 36BC458F6; Tue, 6 Jun 2017 06:21:09 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 6D52758EC; Tue, 6 Jun 2017 06:21:07 +0200 (CEST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jun 2017 21:21:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,304,1493708400"; d="scan'208";a="270637464" Received: from zhangqi.sh.intel.com ([10.239.129.189]) by fmsmga004.fm.intel.com with ESMTP; 05 Jun 2017 21:21:04 -0700 From: Qi Zhang To: jingjing.wu@intel.com, helin.zhang@intel.com Cc: dev@dpdk.org, Qi Zhang , stable@dpdk.org Date: Mon, 5 Jun 2017 17:14:20 -0400 Message-Id: <1496697260-20726-1-git-send-email-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [dpdk-dev] [PATCH] net/i40e: fix VF statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" CRC bytes should be excluded, so rx/tx bytes of VF stats is aligned with PF stats. Fixes: 9aace75fc82e ("i40e: fix statistics") Cc: stable@dpdk.org Signed-off-by: Qi Zhang --- drivers/net/i40e/i40e_ethdev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 4c49673..7aa7f91 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -2329,6 +2329,10 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx), vsi->offset_loaded, &oes->rx_broadcast, &nes->rx_broadcast); + /* exclude CRC bytes */ + nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + + nes->rx_broadcast) * ETHER_CRC_LEN; + i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded, &oes->rx_discards, &nes->rx_discards); /* GLV_REPC not supported */ @@ -2348,6 +2352,9 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx), vsi->offset_loaded, &oes->tx_broadcast, &nes->tx_broadcast); + /* exclude CRC bytes */ + nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast + + nes->tx_broadcast) * ETHER_CRC_LEN; /* GLV_TDPC not supported */ i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, &oes->tx_errors, &nes->tx_errors);