diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 01e20ac..b206b44 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -2040,6 +2040,8 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
 			   "Load request was sent. Load code: 0x%x\n",
 			   load_code);
 
+		ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
+
 		/* CQ75580:
 		 * When coming back from hiberbate state, the registers from
 		 * which shadow is read initially are not initialized. It turns
@@ -2943,6 +2945,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
 {
 	u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
 	u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
+	struct ecore_mcp_link_capabilities *p_caps;
 	struct ecore_mcp_link_params *link;
 	enum _ecore_status_t rc;
 
@@ -3032,6 +3035,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
 
 	/* Read default link configuration */
 	link = &p_hwfn->mcp_info->link_input;
+	p_caps = &p_hwfn->mcp_info->link_capabilities;
 	port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
 	    OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
 	link_temp = ecore_rd(p_hwfn, p_ptt,
@@ -3039,9 +3043,7 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
 			     OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
 	link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
 	link->speed.advertised_speeds = link_temp;
-
-	link_temp = link->speed.advertised_speeds;
-	p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
+	p_caps->speed_capabilities = link->speed.advertised_speeds;
 
 	link_temp = ecore_rd(p_hwfn, p_ptt,
 			     port_cfg_addr +
@@ -3073,10 +3075,8 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
 		DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
 	}
 
-	p_hwfn->mcp_info->link_capabilities.default_speed =
-	    link->speed.forced_speed;
-	p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
-	    link->speed.autoneg;
+	p_caps->default_speed = link->speed.forced_speed;
+	p_caps->default_speed_autoneg = link->speed.autoneg;
 
 	link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
 	link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
@@ -3326,6 +3326,8 @@ static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
 	 */
 	ecore_hw_info_port_num(p_hwfn, p_ptt);
 
+	ecore_mcp_get_capabilities(p_hwfn, p_ptt);
+
 #ifndef ASIC_ONLY
 	if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
 #endif
diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c
index cdb5cf2..1e616ad 100644
--- a/drivers/net/qede/base/ecore_mcp.c
+++ b/drivers/net/qede/base/ecore_mcp.c
@@ -225,7 +225,11 @@ static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 	if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 		p_hwfn->mcp_info->block_mb_sending = false;
 
-	if (p_hwfn->mcp_info->block_mb_sending) {
+	/* There's at least a single command that is sent by ecore during the
+	 * load sequence [expectation of MFW].
+	 */
+	if ((p_hwfn->mcp_info->block_mb_sending) &&
+	    (cmd != DRV_MSG_CODE_FEATURE_SUPPORT)) {
 		DP_NOTICE(p_hwfn, false,
 			  "Trying to send a MFW mailbox command [0x%x]"
 			  " in parallel to [UN]LOAD_REQ. Aborting.\n",
@@ -1202,8 +1206,7 @@ enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
 
 	if (b_up)
 		DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
-			   "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
-			   " adv_speed 0x%08x, loopback 0x%08x\n",
+			   "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
 			   phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
 			   phy_cfg.loopback_mode);
 	else
@@ -3250,3 +3253,36 @@ enum _ecore_status_t
 
 	return ECORE_SUCCESS;
 }
+
+bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
+{
+	return !!(p_hwfn->mcp_info->capabilities &
+		  FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
+}
+
+enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
+						struct ecore_ptt *p_ptt)
+{
+	u32 mcp_resp;
+	enum _ecore_status_t rc;
+
+	rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
+			   0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
+	if (rc == ECORE_SUCCESS)
+		DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
+			   "MFW supported features: %08x\n",
+			   p_hwfn->mcp_info->capabilities);
+
+	return rc;
+}
+
+enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
+						struct ecore_ptt *p_ptt)
+{
+	u32 mcp_resp, mcp_param, features;
+
+	features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ;
+
+	return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
+			     features, &mcp_resp, &mcp_param);
+}
diff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h
index 77fb5a3..5d2f4e5 100644
--- a/drivers/net/qede/base/ecore_mcp.h
+++ b/drivers/net/qede/base/ecore_mcp.h
@@ -60,6 +60,9 @@ struct ecore_mcp_info {
 	u8 *mfw_mb_shadow;
 	u16 mfw_mb_length;
 	u16 mcp_hist;
+
+	/* Capabilties negotiated with the MFW */
+	u32 capabilities;
 };
 
 struct ecore_mcp_mb_params {
@@ -493,4 +496,23 @@ enum _ecore_status_t
 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 		      struct ecore_resc_unlock_params *p_params);
 
+/**
+ * @brief Learn of supported MFW features; To be done during early init
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ */
+enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
+						struct ecore_ptt *p_ptt);
+
+/**
+ * @brief Inform MFW of set of features supported by driver. Should be done
+ * inside the contet of the LOAD_REQ.
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ */
+enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
+						struct ecore_ptt *p_ptt);
+
 #endif /* __ECORE_MCP_H__ */
diff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h
index abc190c..86fa0cb 100644
--- a/drivers/net/qede/base/ecore_mcp_api.h
+++ b/drivers/net/qede/base/ecore_mcp_api.h
@@ -1134,4 +1134,13 @@ enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
 enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn,
 					       struct ecore_ptt *p_ptt);
 
+
+/**
+ * @brief - Return whether management firmware support smart AN
+ *
+ * @param p_hwfn
+ *
+ * @return bool - true iff feature is supported.
+ */
+bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn);
 #endif
diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index f41d4e6..41711cc 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -99,7 +99,7 @@ struct eth_phy_cfg {
 #define EEE_TX_TIMER_USEC_LATENCY_TIME		(0x6000)
 
 	u32 link_modes; /* Additional link modes */
-#define LINK_MODE_SMARTLINQ_ENABLE		0x1
+#define LINK_MODE_SMARTLINQ_ENABLE		0x1  /* XXX Deprecate */
 };
 
 struct port_mf_cfg {
@@ -688,6 +688,7 @@ struct public_port {
 #define LFA_FLOW_CTRL_MISMATCH				(1 << 4)
 #define LFA_ADV_SPEED_MISMATCH				(1 << 5)
 #define LFA_EEE_MISMATCH				(1 << 6)
+#define LFA_LINK_MODES_MISMATCH			(1 << 7)
 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET	8
 #define LINK_FLAP_AVOIDANCE_COUNT_MASK		0x0000ff00
 #define LINK_FLAP_COUNT_OFFSET			16
@@ -1364,10 +1365,10 @@ struct public_drv_mb {
 #define DRV_MB_PARAM_PORT_MASK			0x00600000
 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE		0x002a0000
 
-/* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_*,
- * return FW_MB_PARAM_FEATURE_SUPPORT_*
- */
+/* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */
 #define DRV_MSG_CODE_FEATURE_SUPPORT            0x00300000
+/* return FW_MB_PARAM_FEATURE_SUPPORT_*  */
+#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT	0x00310000
 
 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
 
@@ -1516,10 +1517,14 @@ struct public_drv_mb {
 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT      8
 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK       0x0000FF00
 
-/* driver supports SmartLinQ */
-#define DRV_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ  0x00000001
-/* driver support EEE */
-#define DRV_MB_PARAM_FEATURE_SUPPORT_EEE        0x00000002
+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK      0x0000FFFF
+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SHIFT     0
+/* driver supports SmartLinQ parameter */
+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001
+/* driver supports EEE parameter */
+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE       0x00000002
+#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK      0xFFFF0000
+#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_SHIFT     16
 
 	u32 fw_mb_header;
 #define FW_MSG_CODE_MASK                        0xffff0000
@@ -1636,6 +1641,7 @@ struct public_drv_mb {
 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF
 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT		0
 
+/* get MFW feature support response */
 /* MFW supports SmartLinQ */
 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001
 /* MFW supports EEE */
diff --git a/drivers/net/qede/base/nvm_cfg.h b/drivers/net/qede/base/nvm_cfg.h
index ccd9286..ed024f2 100644
--- a/drivers/net/qede/base/nvm_cfg.h
+++ b/drivers/net/qede/base/nvm_cfg.h
@@ -1165,7 +1165,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
 		#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
 		#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
@@ -1181,7 +1180,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
 		#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
 		#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
@@ -1213,6 +1211,14 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4
 		#define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5
 		#define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6
+		#define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000
+		#define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23
+		#define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0
+		#define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1
+		#define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000
+		#define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24
+		#define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0
+		#define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1
 	u32 phy_cfg; /* 0x1C */
 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
 		#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
@@ -1291,10 +1297,15 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \
 			0x00E00000
 		#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
+		#define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK \
+			0x01000000
+		#define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24
+		#define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED \
+			0x0
+		#define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1
 	u32 mba_cfg2; /* 0x2C */
 		#define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
 		#define NVM_CFG1_PORT_RESERVED65_OFFSET 0
@@ -1457,7 +1468,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
@@ -1468,7 +1478,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_SMARTLINQ 0x8
 	/*  This field defines the board technology
 	 * (backpane,transceiver,external PHY)
 	*/
@@ -1539,7 +1548,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
@@ -1550,7 +1558,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_SMARTLINQ 0x8
 	/*  This field defines the board technology
 	 * (backpane,transceiver,external PHY)
 	*/
@@ -1621,7 +1628,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
@@ -1632,7 +1638,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_SMARTLINQ 0x8
 	/*  This field defines the board technology
 	 * (backpane,transceiver,external PHY)
 	*/
@@ -1705,7 +1710,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
@@ -1716,7 +1720,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_SMARTLINQ 0x8
 	/*  This field defines the board technology
 	 * (backpane,transceiver,external PHY)
 	*/
@@ -1784,7 +1787,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_SMARTLINQ 0x8
 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
@@ -1795,7 +1797,6 @@ struct nvm_cfg1_port {
 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
 		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
-		#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_SMARTLINQ 0x8
 	/*  This field defines the board technology
 	 * (backpane,transceiver,external PHY)
 	*/
diff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h
index 8e0c999..42560d5 100644
--- a/drivers/net/qede/qede_if.h
+++ b/drivers/net/qede/qede_if.h
@@ -44,6 +44,8 @@ struct qed_dev_info {
 	bool tx_switching;
 	u16 mtu;
 
+	bool smart_an;
+
 	/* Out param for qede */
 	bool vxlan_enable;
 	bool gre_enable;
diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c
index 2447ffb..42b556f 100644
--- a/drivers/net/qede/qede_main.c
+++ b/drivers/net/qede/qede_main.c
@@ -335,6 +335,7 @@ static int qed_slowpath_start(struct ecore_dev *edev,
 static int
 qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
 {
+	struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(edev);
 	struct ecore_ptt *ptt = NULL;
 	struct ecore_tunnel_info *tun = &edev->tunnel;
 
@@ -371,6 +372,8 @@ static int qed_slowpath_start(struct ecore_dev *edev,
 		dev_info->mf_mode = edev->mf_mode;
 		dev_info->tx_switching = false;
 
+		dev_info->smart_an = ecore_mcp_is_smart_an_supported(p_hwfn);
+
 		ptt = ecore_ptt_acquire(ECORE_LEADING_HWFN(edev));
 		if (ptt) {
 			ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
