[dpdk-dev,v6,3/3] net/mlx5: add Rx HW timestamp
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Commit Message
Expose Rx HW timestamp to packet mbufs.
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
---
Changes in v6:
- Rebasing the work on top of 217b1421 ("net/mlx5: separate DPDK from Verbs Rx queue objects")
---
drivers/net/mlx5/mlx5_ethdev.c | 3 ++-
drivers/net/mlx5/mlx5_rxq.c | 6 +++++-
drivers/net/mlx5/mlx5_rxtx.c | 5 +++++
drivers/net/mlx5/mlx5_rxtx.h | 3 ++-
drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 13 ++++++++++++-
5 files changed, 26 insertions(+), 4 deletions(-)
Comments
> On Oct 3, 2017, at 4:00 AM, Raslan Darawsheh <rasland@mellanox.com> wrote:
>
> Expose Rx HW timestamp to packet mbufs.
>
> Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
> ---
> Changes in v6:
> - Rebasing the work on top of 217b1421 ("net/mlx5: separate DPDK from Verbs Rx queue objects")
> ---
Raslan,
It looks like you also rebased it on top of my ARM NEON patch set:
[PATCH v1 0/7] net/mlx5: add vectorized Rx/Tx burst for ARM
So, it might not be possible for Ferruh to apply on Nelio's patchset, because
filenames are different.
You can either
1) Rebase it on only Nelio's patchset, then I need to add the timestamp code for
ARM NEON to my patch.
2) Rebase it on my patchset with adding the timestamp code for ARM NEON by
yourself.
I'm okay with both ways.
If you choose 1), I ack this patch.
Acked-by: Yongseok Koh <yskoh@mellanox.com>
Yongseok
@@ -686,7 +686,8 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM) :
0) |
- (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0);
+ (priv->hw_vlan_strip ? DEV_RX_OFFLOAD_VLAN_STRIP : 0) |
+ DEV_RX_OFFLOAD_TIMESTAMP;
if (!priv->mps)
info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
if (priv->hw_csum)
@@ -609,7 +609,7 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
.comp_mask = 0,
};
- if (priv->cqe_comp) {
+ if (priv->cqe_comp && !rxq_data->hw_timestamp) {
attr.cq.ibv.comp_mask |= IBV_CQ_INIT_ATTR_MASK_FLAGS;
attr.cq.mlx5.comp_mask |=
MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
@@ -620,6 +620,8 @@ mlx5_priv_rxq_ibv_new(struct priv *priv, uint16_t idx)
*/
if (rxq_check_vec_support(rxq_data) < 0)
cqe_n *= 2;
+ } else if (priv->cqe_comp && rxq_data->hw_timestamp) {
+ DEBUG("Rx CQE compression is disabled for HW timestamp");
}
tmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,
&attr.cq.mlx5));
@@ -936,6 +938,8 @@ mlx5_priv_rxq_new(struct priv *priv, uint16_t idx, uint16_t desc,
if (priv->hw_csum_l2tun)
tmpl->rxq.csum_l2tun =
!!dev->data->dev_conf.rxmode.hw_ip_checksum;
+ tmpl->rxq.hw_timestamp =
+ !!dev->data->dev_conf.rxmode.hw_timestamp;
/* Configure VLAN stripping. */
tmpl->rxq.vlan_strip = (priv->hw_vlan_strip &&
!!dev->data->dev_conf.rxmode.hw_vlan_strip);
@@ -1887,6 +1887,11 @@ mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
pkt->vlan_tci =
rte_be_to_cpu_16(cqe->vlan_info);
}
+ if (rxq->hw_timestamp) {
+ pkt->timestamp =
+ rte_be_to_cpu_64(cqe->timestamp);
+ pkt->ol_flags |= PKT_RX_TIMESTAMP;
+ }
if (rxq->crc_present)
len -= ETHER_CRC_LEN;
PKT_LEN(pkt) = len;
@@ -106,6 +106,7 @@ struct rxq_zip {
struct mlx5_rxq_data {
unsigned int csum:1; /* Enable checksum offloading. */
unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
+ unsigned int hw_timestamp:1; /* Enable HW timestamp. */
unsigned int vlan_strip:1; /* Enable VLAN stripping. */
unsigned int crc_present:1; /* CRC must be subtracted. */
unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
@@ -115,7 +116,7 @@ struct mlx5_rxq_data {
unsigned int rss_hash:1; /* RSS hash result is enabled. */
unsigned int mark:1; /* Marked flow available on the queue. */
unsigned int pending_err:1; /* CQE error needs to be handled. */
- unsigned int :7; /* Remaining bits. */
+ unsigned int :6; /* Remaining bits. */
volatile uint32_t *rq_db;
volatile uint32_t *cq_db;
uint16_t rq_ci;
@@ -545,7 +545,8 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],
{
__m128i pinfo0, pinfo1;
__m128i pinfo, ptype;
- __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
+ __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |
+ rxq->hw_timestamp * PKT_RX_TIMESTAMP);
__m128i cv_flags;
const __m128i zero = _mm_setzero_si128();
const __m128i ptype_mask =
@@ -938,6 +939,16 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
/* D.5 fill in mbuf - rearm_data and packet_type. */
rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
+ if (rxq->hw_timestamp) {
+ pkts[pos]->timestamp =
+ rte_be_to_cpu_64(cq[pos].timestamp);
+ pkts[pos + 1]->timestamp =
+ rte_be_to_cpu_64(cq[pos + p1].timestamp);
+ pkts[pos + 2]->timestamp =
+ rte_be_to_cpu_64(cq[pos + p2].timestamp);
+ pkts[pos + 3]->timestamp =
+ rte_be_to_cpu_64(cq[pos + p3].timestamp);
+ }
#ifdef MLX5_PMD_SOFT_COUNTERS
/* Add up received bytes count. */
byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);