From patchwork Sun Feb 11 06:55:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xing, Beilei" X-Patchwork-Id: 35108 X-Patchwork-Delegate: helin.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CF94C1B333; Sun, 11 Feb 2018 07:55:19 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id BD5D91B331 for ; Sun, 11 Feb 2018 07:55:17 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2018 22:55:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,494,1511856000"; d="scan'208";a="26431994" Received: from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52]) by FMSMGA003.fm.intel.com with ESMTP; 10 Feb 2018 22:55:16 -0800 From: Beilei Xing To: qi.z.zhang@intel.com Cc: dev@dpdk.org Date: Sun, 11 Feb 2018 14:55:50 +0800 Message-Id: <1518332150-85375-1-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 2.5.5 Subject: [dpdk-dev] [PATCH] net/i40e: add log when setting input set X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds log when setting input set since global configuration is changed. Signed-off-by: Beilei Xing Reviewed-by: Kirill Rybalchenko Acked-by: Qi Zhang --- drivers/net/i40e/rte_pmd_i40e.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c index dae59e6..1288c51 100644 --- a/drivers/net/i40e/rte_pmd_i40e.c +++ b/drivers/net/i40e/rte_pmd_i40e.c @@ -3071,6 +3071,7 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype, { struct rte_eth_dev *dev; struct i40e_hw *hw; + struct i40e_pf *pf; uint64_t inset_reg; uint32_t mask_reg[2]; int i; @@ -3086,6 +3087,12 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype, return -EINVAL; hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); + + if (pf->support_multi_driver) { + PMD_DRV_LOG(ERR, "Input set configuration is not supported."); + return -ENOTSUP; + } /* Clear mask first */ for (i = 0; i < 2; i++) @@ -3098,14 +3105,17 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype, switch (inset_type) { case INSET_HASH: - i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype), - (uint32_t)(inset_reg & UINT32_MAX)); - i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), - (uint32_t)((inset_reg >> - I40E_32_BIT_WIDTH) & UINT32_MAX)); + i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype), + (uint32_t)(inset_reg & UINT32_MAX)); + i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), + (uint32_t)((inset_reg >> + I40E_32_BIT_WIDTH) & UINT32_MAX)); for (i = 0; i < 2; i++) - i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), - mask_reg[i]); + i40e_check_write_global_reg(hw, + I40E_GLQF_HASH_MSK(i, pctype), + mask_reg[i]); + i40e_global_cfg_warning(I40E_WARNING_HASH_INSET); + i40e_global_cfg_warning(I40E_WARNING_HASH_MSK); break; case INSET_FDIR: i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), @@ -3114,8 +3124,10 @@ rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype, (uint32_t)((inset_reg >> I40E_32_BIT_WIDTH) & UINT32_MAX)); for (i = 0; i < 2; i++) - i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), - mask_reg[i]); + i40e_check_write_global_reg(hw, + I40E_GLQF_FD_MSK(i, pctype), + mask_reg[i]); + i40e_global_cfg_warning(I40E_WARNING_FD_MSK); break; case INSET_FDIR_FLX: i40e_check_write_reg(hw, I40E_PRTQF_FD_FLXINSET(pctype),