From patchwork Mon Aug 13 12:57:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ZY Qiu X-Patchwork-Id: 43687 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E11FC37AF; Mon, 13 Aug 2018 14:58:08 +0200 (CEST) Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by dpdk.org (Postfix) with ESMTP id 2CFCB37A2 for ; Mon, 13 Aug 2018 14:58:07 +0200 (CEST) Received: by mail-pf1-f194.google.com with SMTP id y10-v6so7614426pfn.8 for ; Mon, 13 Aug 2018 05:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=slj5GlP2i89Z6gFnDnu95dGOETjAdsvaS5cky89EehI=; b=Ayr1E4n/ncGDNh3exkIdCkpzsvNql5XianpcvBWmUinEHFVtsV6bdVmonIp8bUSr6J +dEQC9sx6iAlxu0BMxnu5q5CHwIHRbrovtbf6xAuYtK12OwXFhmVod/IdNscWgJpm9r4 MVYi1MAauGXgTeGy91vcX7gCt5j4vstibBYXLJpiw7slmAVuTZnbnmLUWXlsuUBI8fOv fzwbt+mwMrlGpOGo9LRlMyVrE2h1qwSlsQXIwca3G+oBv4tc7oF0pPuWYsQ6GdQmSCmf 3qrwEOqltBCT/1y6mHciHkxvKmgeFp3Eo0iBhs2DDfXaFffWf8hY+Kf9OqhxvH/a6QwU 9lEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=slj5GlP2i89Z6gFnDnu95dGOETjAdsvaS5cky89EehI=; b=RezXPsRxLOOkvw87GDMQoCXzuym2ZltxHsNSnzBIMPZdnaH6erOVRQN9BXb87+/kWh z38en86eoh5tqX/SN4Z5HiUzuXZkyhd+L2BF6lCSfjsWdXD+HoeL9uVg6VCeKPHYCNom os72lGuTG5zHa3RMJ4MIIzd3ngk5z8BU80a/WzHShwS1luV41zDlxCoY9MJw8mNf3i+x S7zL0T5J+3fFTl0csDCVm+czqqR+nWWrChrjDSxfzwwlJKSOx32zLZioP2hu9Cjz+5DE XSftpGIj624f0SfR0fP+t37saEbv8Uwlkjk6lANoxdCMwd22t4SkP22c292xe40ZNkH9 OrTA== X-Gm-Message-State: AOUpUlHDdmpWiT6OHTrtw/LV46l/n/yg/BFszkuLfiMdnN1fM6BWa8Df sJcvQp+1I4ubMFA/EoKXsf+c3OVl X-Google-Smtp-Source: AA+uWPyPiJ0MnkExERPH0UirEeIEzyq3JQ8O5XrWiEu5fUmvSZa5+Md/1/vq4GfrKzwyacCaNkIKsA== X-Received: by 2002:a65:5803:: with SMTP id g3-v6mr17274075pgr.117.1534165085958; Mon, 13 Aug 2018 05:58:05 -0700 (PDT) Received: from localhost.localdomain ([43.245.220.91]) by smtp.gmail.com with ESMTPSA id z20-v6sm41911352pfd.99.2018.08.13.05.58.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Aug 2018 05:58:05 -0700 (PDT) From: Drocula To: Cc: dev@dpdk.org, anatoly.burakov@intel.com, stephen@networkplumber.org, Drocula Date: Mon, 13 Aug 2018 12:57:48 +0000 Message-Id: <1534165068-23161-1-git-send-email-quzeyao@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1533494497-16253-1-git-send-email-quzeyao@gmail.com> References: <1533494497-16253-1-git-send-email-quzeyao@gmail.com> Subject: [dpdk-dev] [PATCH v2] bus/pci: check if 5-level paging is enabled when testing IOMMU address width X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The kernel version 4.14 released with the support of 5-level paging. When PML5 enabled, user-space virtual addresses uses up to 56 bits. see kernel's Documentation/x86/x86_64/mm.txt. Signed-off-by: ZY Qiu --- drivers/bus/pci/linux/pci.c | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index 04648ac..acc19df 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -552,16 +553,39 @@ } #if defined(RTE_ARCH_X86) +/* + * Try to detect whether the system uses 5-level page table. + */ +static bool +system_uses_PML5(void) +{ +#define X86_56_BIT_VA (0xfULL << 52) + void *page_4k; + page_4k = mmap((void *)X86_56_BIT_VA, 4096, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + + if (page_4k == MAP_FAILED) + return false; + munmap(page_4k, 4096); + + if ((unsigned long long)page_4k & X86_56_BIT_VA) + return true; + return false; +} + static bool pci_one_device_iommu_support_va(struct rte_pci_device *dev) { #define VTD_CAP_MGAW_SHIFT 16 #define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) -#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */ +/* From Documentation/x86/x86_64/mm.txt */ +#define X86_VA_WIDTH_PML4 47 +#define X86_VA_WIDTH_PML5 56 + struct rte_pci_addr *addr = &dev->addr; char filename[PATH_MAX]; FILE *fp; - uint64_t mgaw, vtd_cap_reg = 0; + uint64_t mgaw, vtd_cap_reg = 0, va_width = X86_VA_WIDTH_PML4; snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", @@ -587,8 +611,11 @@ fclose(fp); + if (system_uses_PML5()) + va_width = X86_VA_WIDTH_PML5; + mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1; - if (mgaw < X86_VA_WIDTH) + if (mgaw < va_width) return false; return true;