From patchwork Tue Nov 5 08:01:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 62424 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62C66A0352; Tue, 5 Nov 2019 09:02:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 484B51BDAC; Tue, 5 Nov 2019 09:02:13 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 63180493D for ; Tue, 5 Nov 2019 09:02:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@mellanox.com) with ESMTPS (AES256-SHA encrypted); 5 Nov 2019 10:02:07 +0200 Received: from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx [10.210.16.104]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id xA5827LI026479; Tue, 5 Nov 2019 10:02:07 +0200 Received: from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id xA5827OW030766; Tue, 5 Nov 2019 08:02:07 GMT Received: (from viacheslavo@localhost) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id xA5827Qo030765; Tue, 5 Nov 2019 08:02:07 GMT X-Authentication-Warning: pegasus11.mtr.labs.mlnx: viacheslavo set sender to viacheslavo@mellanox.com using -f From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: matan@mellanox.com, rasland@mellanox.com, thomas@monjalon.net, orika@mellanox.com, Yongseok Koh Date: Tue, 5 Nov 2019 08:01:41 +0000 Message-Id: <1572940915-29416-7-git-send-email-viacheslavo@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1572940915-29416-1-git-send-email-viacheslavo@mellanox.com> References: <1572940915-29416-1-git-send-email-viacheslavo@mellanox.com> Subject: [dpdk-dev] [PATCH 06/20] net/mlx5: update meta register matcher set X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introduce the dedicated matcher register field setup routine. Update the code to use this unified one. Signed-off-by: Yongseok Koh Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow_dv.c | 171 +++++++++++++++++++--------------------- 1 file changed, 82 insertions(+), 89 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 019c9b3..eb7e481 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -4903,6 +4903,78 @@ struct field_modify_info modify_tcp[] = { } /** + * Add metadata register item to matcher + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] reg_type + * Type of device metadata register + * @param[in] value + * Register value + * @param[in] mask + * Register mask + */ +static void +flow_dv_match_meta_reg(void *matcher, void *key, + enum modify_reg reg_type, + uint32_t data, uint32_t mask) +{ + void *misc2_m = + MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); + void *misc2_v = + MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); + + data &= mask; + switch (reg_type) { + case REG_A: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data); + break; + case REG_B: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data); + break; + case REG_C_0: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data); + break; + case REG_C_1: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data); + break; + case REG_C_2: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data); + break; + case REG_C_3: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data); + break; + case REG_C_4: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data); + break; + case REG_C_5: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data); + break; + case REG_C_6: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data); + break; + case REG_C_7: + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask); + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data); + break; + default: + assert(false); + break; + } +} + +/** * Add META item to matcher * * @param[in, out] matcher @@ -4920,21 +4992,15 @@ struct field_modify_info modify_tcp[] = { { const struct rte_flow_item_meta *meta_m; const struct rte_flow_item_meta *meta_v; - void *misc2_m = - MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); - void *misc2_v = - MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); meta_m = (const void *)item->mask; if (!meta_m) meta_m = &rte_flow_item_meta_mask; meta_v = (const void *)item->spec; - if (meta_v) { - MLX5_SET(fte_match_set_misc2, misc2_m, - metadata_reg_a, meta_m->data); - MLX5_SET(fte_match_set_misc2, misc2_v, - metadata_reg_a, meta_v->data & meta_m->data); - } + if (meta_v) + flow_dv_match_meta_reg(matcher, key, REG_A, + rte_cpu_to_be_32(meta_v->data), + rte_cpu_to_be_32(meta_m->data)); } /** @@ -4951,13 +5017,7 @@ struct field_modify_info modify_tcp[] = { flow_dv_translate_item_meta_vport(void *matcher, void *key, uint32_t value, uint32_t mask) { - void *misc2_m = - MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); - void *misc2_v = - MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); - - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value); + flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask); } /** @@ -4971,81 +5031,14 @@ struct field_modify_info modify_tcp[] = { * Flow pattern to translate. */ static void -flow_dv_translate_item_tag(void *matcher, void *key, - const struct rte_flow_item *item) +flow_dv_translate_mlx5_item_tag(void *matcher, void *key, + const struct rte_flow_item *item) { - void *misc2_m = - MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); - void *misc2_v = - MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); const struct mlx5_rte_flow_item_tag *tag_v = item->spec; const struct mlx5_rte_flow_item_tag *tag_m = item->mask; enum modify_reg reg = tag_v->id; - rte_be32_t value = tag_v->data; - rte_be32_t mask = tag_m->data; - switch (reg) { - case REG_A: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, - rte_be_to_cpu_32(value)); - break; - case REG_B: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, - rte_be_to_cpu_32(value)); - break; - case REG_C_0: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, - rte_be_to_cpu_32(value)); - break; - case REG_C_1: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, - rte_be_to_cpu_32(value)); - break; - case REG_C_2: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, - rte_be_to_cpu_32(value)); - break; - case REG_C_3: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, - rte_be_to_cpu_32(value)); - break; - case REG_C_4: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, - rte_be_to_cpu_32(value)); - break; - case REG_C_5: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, - rte_be_to_cpu_32(value)); - break; - case REG_C_6: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, - rte_be_to_cpu_32(value)); - break; - case REG_C_7: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, - rte_be_to_cpu_32(mask)); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, - rte_be_to_cpu_32(value)); - break; - } + flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data); } /** @@ -6177,8 +6170,8 @@ struct field_modify_info modify_tcp[] = { last_item = MLX5_FLOW_LAYER_ICMP6; break; case MLX5_RTE_FLOW_ITEM_TYPE_TAG: - flow_dv_translate_item_tag(match_mask, match_value, - items); + flow_dv_translate_mlx5_item_tag(match_mask, + match_value, items); last_item = MLX5_FLOW_ITEM_TAG; break; case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE: