From patchwork Thu Feb 20 12:44:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 65960 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 33B6EA0556; Thu, 20 Feb 2020 13:44:42 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 068C31C07D; Thu, 20 Feb 2020 13:44:42 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 2B5DA1C07B for ; Thu, 20 Feb 2020 13:44:41 +0100 (CET) Received: from Internal Mail-Server by MTLPINE2 (envelope-from viacheslavo@mellanox.com) with ESMTPS (AES256-SHA encrypted); 20 Feb 2020 14:44:38 +0200 Received: from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx [10.210.16.104]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 01KCicBf006647; Thu, 20 Feb 2020 14:44:38 +0200 Received: from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 01KCicZa008629; Thu, 20 Feb 2020 12:44:38 GMT Received: (from viacheslavo@localhost) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 01KCicHk008628; Thu, 20 Feb 2020 12:44:38 GMT X-Authentication-Warning: pegasus11.mtr.labs.mlnx: viacheslavo set sender to viacheslavo@mellanox.com using -f From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: matan@mellanox.com, rasland@mellanox.com, orika@mellanox.com Date: Thu, 20 Feb 2020 12:44:37 +0000 Message-Id: <1582202677-8591-1-git-send-email-viacheslavo@mellanox.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH] doc/mlx5: clarify memory write combining attribute X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Just add the words about write combining attribute. Signed-off-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 5ab7c07..dd2fbde 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -568,16 +568,17 @@ Run-time configuration The rdma core library can map doorbell register in two ways, depending on the environment variable "MLX5_SHUT_UP_BF": - - As regular cached memory, if the variable is either missing or set to zero. + - As regular cached memory (usually with write combining attribute), if the + variable is either missing or set to zero. - As non-cached memory, if the variable is present and set to not "0" value. The type of mapping may slightly affect the Tx performance, the optimal choice is strongly relied on the host architecture and should be deduced practically. If ``tx_db_nc`` is set to zero, the doorbell is forced to be mapped to regular - memory, the PMD will perform the extra write memory barrier after writing to - doorbell, it might increase the needed CPU clocks per packet to send, but - latency might be improved. + memory (with write combining), the PMD will perform the extra write memory barrier + after writing to doorbell, it might increase the needed CPU clocks per packet + to send, but latency might be improved. If ``tx_db_nc`` is set to one, the doorbell is forced to be mapped to non cached memory, the PMD will not perform the extra write memory barrier