| Message ID | 1594996104-372-2-git-send-email-viacheslavo@mellanox.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Delegated to: | Raslan Darawsheh |
| Headers | show |
| Series | [1/3] net/mlx5: fix compilation issue with missing DevX event | expand |
| Context | Check | Description |
|---|---|---|
| ci/Intel-compilation | success | Compilation OK |
| ci/checkpatch | success | coding style OK |
17/07/2020 16:28, Viacheslav Ovsiienko: > For naw the rte_atomic128_cmp_exchange() is available on x86-64 Typo: now > and ARM64 architectures. The patch fixes the compilation condition > for the code using this atomic transaction. What is fixed exactly? How "not (ppc or 32)" is different of "x86_64 or arm64"? > -#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_32) > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) > + rte_int128_t src; > + > + memset(&src, 0, sizeof(src)); > + *ts = src; > + /* if (*from == *ts) *from = *src else *ts = *from; */ > + rte_atomic128_cmp_exchange(from, ts, &src, 0, > + __ATOMIC_RELAXED, __ATOMIC_RELAXED); > +#else > rte_atomic64_t *cqe = (rte_atomic64_t *)from; > > /* Power architecture does not support 16B compare-and-swap. */ > @@ -665,14 +673,6 @@ > ps[1] = op; > return; > } > -#else > - rte_int128_t src; > - > - memset(&src, 0, sizeof(src)); > - *ts = src; > - /* if (*from == *ts) *from = *src else *ts = *from; */ > - rte_atomic128_cmp_exchange(from, ts, &src, 0, > - __ATOMIC_RELAXED, __ATOMIC_RELAXED); > #endif
> -----Original Message----- > From: Thomas Monjalon <thomas@monjalon.net> > Sent: Friday, July 17, 2020 18:08 > To: Slava Ovsiienko <viacheslavo@mellanox.com> > Cc: dev@dpdk.org; Matan Azrad <matan@mellanox.com>; Raslan > Darawsheh <rasland@mellanox.com> > Subject: Re: [PATCH 2/3] net/mlx5: fix compilation issue with atomic128 > exchange > > 17/07/2020 16:28, Viacheslav Ovsiienko: > > For naw the rte_atomic128_cmp_exchange() is available on x86-64 > > Typo: now > > > and ARM64 architectures. The patch fixes the compilation condition for > > the code using this atomic transaction. > > What is fixed exactly? > How "not (ppc or 32)" is different of "x86_64 or arm64"? CI detected the cases when rte_atomic128_cmp_exchange() is not defined. So, we changed the case: "do not use cas_128 for the PPC and 32-bit and engage one otherwise" to "use cas_128 for x86_64 and ARM64 only, where it is known this one is defined, otherwise - do not engage" With best regards, Slava > > > -#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_32) > > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) > > + rte_int128_t src; > > + > > + memset(&src, 0, sizeof(src)); > > + *ts = src; > > + /* if (*from == *ts) *from = *src else *ts = *from; */ > > + rte_atomic128_cmp_exchange(from, ts, &src, 0, > > + __ATOMIC_RELAXED, > __ATOMIC_RELAXED); #else > > rte_atomic64_t *cqe = (rte_atomic64_t *)from; > > > > /* Power architecture does not support 16B compare-and-swap. */ > @@ > > -665,14 +673,6 @@ > > ps[1] = op; > > return; > > } > > -#else > > - rte_int128_t src; > > - > > - memset(&src, 0, sizeof(src)); > > - *ts = src; > > - /* if (*from == *ts) *from = *src else *ts = *from; */ > > - rte_atomic128_cmp_exchange(from, ts, &src, 0, > > - __ATOMIC_RELAXED, > __ATOMIC_RELAXED); > > #endif > >
diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index 42776b8..cdb0079 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -644,7 +644,15 @@ * update by hardware with soecified rate. We have to * read timestump and WQE completion index atomically. */ -#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_32) +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) + rte_int128_t src; + + memset(&src, 0, sizeof(src)); + *ts = src; + /* if (*from == *ts) *from = *src else *ts = *from; */ + rte_atomic128_cmp_exchange(from, ts, &src, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED); +#else rte_atomic64_t *cqe = (rte_atomic64_t *)from; /* Power architecture does not support 16B compare-and-swap. */ @@ -665,14 +673,6 @@ ps[1] = op; return; } -#else - rte_int128_t src; - - memset(&src, 0, sizeof(src)); - *ts = src; - /* if (*from == *ts) *from = *src else *ts = *from; */ - rte_atomic128_cmp_exchange(from, ts, &src, 0, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); #endif }
For naw the rte_atomic128_cmp_exchange() is available on x86-64 and ARM64 architectures. The patch fixes the compilation condition for the code using this atomic transaction. Fixes: 244788055199 ("net/mlx5: introduce clock queue service routine") Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> --- drivers/net/mlx5/mlx5_txpp.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)