common/mlx5: fix user mode register access command
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Commit Message
To detect the timestamp mode configured on the NIC the mlx5
PMD uses the firmware command ACCESS_REGISTER_USER. This
command is relatively new and might be not supported by
older firmware versions and was rejected, causing annoying
messages in kernel log.
This patch adds the attribute flag check whether firmware
supports the command and avoid the call if it does not.
Fixes: bb7ef9a96281 ("common/mlx5: add register access DevX routine")
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
drivers/common/mlx5/mlx5_prm.h | 3 ++-
drivers/net/mlx5/linux/mlx5_os.c | 7 ++++---
4 files changed, 9 insertions(+), 4 deletions(-)
Comments
Hi,
> -----Original Message-----
> From: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> Sent: Wednesday, July 29, 2020 3:29 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@mellanox.com>; Raslan Darawsheh
> <rasland@mellanox.com>; Dekel Peled <dekelp@mellanox.com>
> Subject: [PATCH] common/mlx5: fix user mode register access command
>
> To detect the timestamp mode configured on the NIC the mlx5
> PMD uses the firmware command ACCESS_REGISTER_USER. This
> command is relatively new and might be not supported by
> older firmware versions and was rejected, causing annoying
> messages in kernel log.
>
> This patch adds the attribute flag check whether firmware
> supports the command and avoid the call if it does not.
>
> Fixes: bb7ef9a96281 ("common/mlx5: add register access DevX routine")
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> ---
> drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
> drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
> drivers/common/mlx5/mlx5_prm.h | 3 ++-
> drivers/net/mlx5/linux/mlx5_os.c | 7 ++++---
> 4 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index d1c674c..7c81ae1 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -688,6 +688,8 @@ struct mlx5_devx_obj *
> relaxed_ordering_write);
> attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
> relaxed_ordering_read);
> + attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
> + access_register_user);
> attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
> eth_net_offloads);
> attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
> b/drivers/common/mlx5/mlx5_devx_cmds.h
> index 528cb7b..1c84cea 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> @@ -93,6 +93,7 @@ struct mlx5_hca_attr {
> uint32_t vhca_id:16;
> uint32_t relaxed_ordering_write:1;
> uint32_t relaxed_ordering_read:1;
> + uint32_t access_register_user:1;
> uint32_t wqe_index_ignore:1;
> uint32_t cross_channel:1;
> uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
> diff --git a/drivers/common/mlx5/mlx5_prm.h
> b/drivers/common/mlx5/mlx5_prm.h
> index 62efa72..0fa42bb 100644
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -1104,7 +1104,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
> u8 log_max_eq_sz[0x8];
> u8 relaxed_ordering_write[0x1];
> u8 relaxed_ordering_read[0x1];
> - u8 log_max_mkey[0x6];
> + u8 access_register_user[0x1];
> + u8 log_max_mkey[0x5];
> u8 reserved_at_f0[0x8];
> u8 dump_fill_mkey[0x1];
> u8 reserved_at_f9[0x3];
> diff --git a/drivers/net/mlx5/linux/mlx5_os.c
> b/drivers/net/mlx5/linux/mlx5_os.c
> index fa3b027..c0d5325 100644
> --- a/drivers/net/mlx5/linux/mlx5_os.c
> +++ b/drivers/net/mlx5/linux/mlx5_os.c
> @@ -1067,9 +1067,10 @@
> if (config->devx) {
> uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
>
> - err = mlx5_devx_cmd_register_read
> - (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
> - reg, MLX5_ST_SZ_DW(register_mtutc));
> + err = config->hca_attr.access_register_user ?
> + mlx5_devx_cmd_register_read
> + (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
> + reg, MLX5_ST_SZ_DW(register_mtutc)) :
> ENOTSUP;
> if (!err) {
> uint32_t ts_mode;
>
> --
> 1.8.3.1
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
@@ -688,6 +688,8 @@ struct mlx5_devx_obj *
relaxed_ordering_write);
attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
relaxed_ordering_read);
+ attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
+ access_register_user);
attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
eth_net_offloads);
attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
@@ -93,6 +93,7 @@ struct mlx5_hca_attr {
uint32_t vhca_id:16;
uint32_t relaxed_ordering_write:1;
uint32_t relaxed_ordering_read:1;
+ uint32_t access_register_user:1;
uint32_t wqe_index_ignore:1;
uint32_t cross_channel:1;
uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
@@ -1104,7 +1104,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 log_max_eq_sz[0x8];
u8 relaxed_ordering_write[0x1];
u8 relaxed_ordering_read[0x1];
- u8 log_max_mkey[0x6];
+ u8 access_register_user[0x1];
+ u8 log_max_mkey[0x5];
u8 reserved_at_f0[0x8];
u8 dump_fill_mkey[0x1];
u8 reserved_at_f9[0x3];
@@ -1067,9 +1067,10 @@
if (config->devx) {
uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
- err = mlx5_devx_cmd_register_read
- (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
- reg, MLX5_ST_SZ_DW(register_mtutc));
+ err = config->hca_attr.access_register_user ?
+ mlx5_devx_cmd_register_read
+ (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
+ reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
if (!err) {
uint32_t ts_mode;