diff mbox series

[v9,14/14] config: fix Arm implementer and its SoCs

Message ID 1605100718-7991-15-git-send-email-juraj.linkes@pantheon.tech (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series Arm build options rework |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/travis-robot warning Travis build: failed
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS

Commit Message

Juraj Linkeš Nov. 11, 2020, 1:18 p.m. UTC 
Fix the implementer and part number of DPAA and ARMADA SoCs.
The current values of 16 cores and 1 NUMA node don't cover all SoCs from
the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
Increase these to 64 and 4 to widen the coverage.
Add configuration to SoC options where smaller values are needed.

Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
---
 config/arm/meson.build | 54 ++++++++++++++++++------------------------
 1 file changed, 23 insertions(+), 31 deletions(-)

Comments

Honnappa Nagarahalli Nov. 13, 2020, 6:05 a.m. UTC | #1 
<snip>

Hi Juraj,
	The failure in Travis should be fixed by [1]. I think you can include it in this series so that we get a clean build in Travis.

Ajit, Hemant, Vimal, Thomas,
	Appreciate if you could test this series on your respective platforms.

We need testing on x86 as well.

[1] http://patches.dpdk.org/patch/84054/

> 
> Fix the implementer and part number of DPAA and ARMADA SoCs.
> The current values of 16 cores and 1 NUMA node don't cover all SoCs from
> the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
> Increase these to 64 and 4 to widen the coverage.
> Add configuration to SoC options where smaller values are needed.
> 
> Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>

> ---
>  config/arm/meson.build | 54 ++++++++++++++++++------------------------
>  1 file changed, 23 insertions(+), 31 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> d991f9954..b06dfb5ed 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -75,8 +75,8 @@ implementer_arm = {
>  		['RTE_MACHINE', '"armv8a"'],
>  		['RTE_USE_C11_MEM_MODEL', true],
>  		['RTE_CACHE_LINE_SIZE', 64],
> -		['RTE_MAX_LCORE', 16],
> -		['RTE_MAX_NUMA_NODES', 1]
> +		['RTE_MAX_LCORE', 64],
> +		['RTE_MAX_NUMA_NODES', 4]
>  	],
>  	'part_number_config': part_number_config_arm  } @@ -146,38
> +146,12 @@ implementer_ampere = {
>  	}
>  }
> 
> -implementer_marvell = {
> -	'description': 'Marvell ARMADA',
> -	'flags': [
> -		['RTE_MACHINE', '"armv8a"'],
> -		['RTE_CACHE_LINE_SIZE', 64],
> -		['RTE_MAX_LCORE', 16],
> -		['RTE_MAX_NUMA_NODES', 1]
> -	],
> -	'part_number_config': part_number_config_arm
> -}
> -
> -implementer_dpaa = {
> -	'description': 'NXP DPAA',
> -	'flags': [
> -		['RTE_MACHINE', '"dpaa"'],
> -		['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
> -		['RTE_USE_C11_MEM_MODEL', true],
> -		['RTE_CACHE_LINE_SIZE', 64],
> -		['RTE_MAX_LCORE', 16],
> -		['RTE_MAX_NUMA_NODES', 1]
> -	],
> -	'part_number_config': part_number_config_arm
> -}
> -
>  ## Arm implementers (ID from MIDR in Arm Architecture Reference
> Manual)  implementers = {
>  	'generic': implementer_generic,
>  	'0x41': implementer_arm,
>  	'0x43': implementer_cavium,
> -	'0x50': implementer_ampere,
> -	'0x56': implementer_marvell,
> -	'dpaa': implementer_dpaa
> +	'0x50': implementer_ampere
>  }
> 
>  # soc specific aarch64 flags have the highest priority @@ -190,8 +164,12 @@
> soc_generic = {
> 
>  soc_armada = {
>  	'description': 'Marvell ARMADA',
> -	'implementer': '0x56',
> +	'implementer': '0x41',
>  	'part_number': '0xd08',
> +	'flags': [
> +		['RTE_MAX_LCORE', 16],
> +		['RTE_MAX_NUMA_NODES', 1]
> +	],
>  	'numa': false,
>  	'disabled_drivers': ['bus/dpaa', 'bus/fslmc', 'common/dpaax']  } @@ -
> 200,13 +178,23 @@ soc_bluefield = {
>  	'description': 'NVIDIA BlueField',
>  	'implementer': '0x41',
>  	'part_number': '0xd08',
> +	'flags': [
> +		['RTE_MAX_LCORE', 16],
> +		['RTE_MAX_NUMA_NODES', 1]
> +	],
>  	'numa': false
>  }
> 
>  soc_dpaa = {
>  	'description': 'NXP DPAA',
> -	'implementer': 'dpaa',
> +	'implementer': '0x41',
>  	'part_number': '0xd08',
> +	'flags': [
> +		['RTE_MACHINE', '"dpaa"'],
> +		['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
> +		['RTE_MAX_LCORE', 16],
> +		['RTE_MAX_NUMA_NODES', 1]
> +	],
>  	'numa': false
>  }
> 
> @@ -243,6 +231,10 @@ soc_octeontx2 = {
>  soc_stingray = {
>  	'description': 'Broadcom Stingray',
>  	'implementer': '0x41',
> +	'flags': [
> +		['RTE_MAX_LCORE', 16],
> +		['RTE_MAX_NUMA_NODES', 1]
> +	],
>  	'part_number': '0xd08',
>  	'numa': false
>  }
> --
> 2.20.1
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index d991f9954..b06dfb5ed 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -75,8 +75,8 @@  implementer_arm = {
 		['RTE_MACHINE', '"armv8a"'],
 		['RTE_USE_C11_MEM_MODEL', true],
 		['RTE_CACHE_LINE_SIZE', 64],
-		['RTE_MAX_LCORE', 16],
-		['RTE_MAX_NUMA_NODES', 1]
+		['RTE_MAX_LCORE', 64],
+		['RTE_MAX_NUMA_NODES', 4]
 	],
 	'part_number_config': part_number_config_arm
 }
@@ -146,38 +146,12 @@  implementer_ampere = {
 	}
 }
 
-implementer_marvell = {
-	'description': 'Marvell ARMADA',
-	'flags': [
-		['RTE_MACHINE', '"armv8a"'],
-		['RTE_CACHE_LINE_SIZE', 64],
-		['RTE_MAX_LCORE', 16],
-		['RTE_MAX_NUMA_NODES', 1]
-	],
-	'part_number_config': part_number_config_arm
-}
-
-implementer_dpaa = {
-	'description': 'NXP DPAA',
-	'flags': [
-		['RTE_MACHINE', '"dpaa"'],
-		['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
-		['RTE_USE_C11_MEM_MODEL', true],
-		['RTE_CACHE_LINE_SIZE', 64],
-		['RTE_MAX_LCORE', 16],
-		['RTE_MAX_NUMA_NODES', 1]
-	],
-	'part_number_config': part_number_config_arm
-}
-
 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
 implementers = {
 	'generic': implementer_generic,
 	'0x41': implementer_arm,
 	'0x43': implementer_cavium,
-	'0x50': implementer_ampere,
-	'0x56': implementer_marvell,
-	'dpaa': implementer_dpaa
+	'0x50': implementer_ampere
 }
 
 # soc specific aarch64 flags have the highest priority
@@ -190,8 +164,12 @@  soc_generic = {
 
 soc_armada = {
 	'description': 'Marvell ARMADA',
-	'implementer': '0x56',
+	'implementer': '0x41',
 	'part_number': '0xd08',
+	'flags': [
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'numa': false,
 	'disabled_drivers': ['bus/dpaa', 'bus/fslmc', 'common/dpaax']
 }
@@ -200,13 +178,23 @@  soc_bluefield = {
 	'description': 'NVIDIA BlueField',
 	'implementer': '0x41',
 	'part_number': '0xd08',
+	'flags': [
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'numa': false
 }
 
 soc_dpaa = {
 	'description': 'NXP DPAA',
-	'implementer': 'dpaa',
+	'implementer': '0x41',
 	'part_number': '0xd08',
+	'flags': [
+		['RTE_MACHINE', '"dpaa"'],
+		['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'numa': false
 }
 
@@ -243,6 +231,10 @@  soc_octeontx2 = {
 soc_stingray = {
 	'description': 'Broadcom Stingray',
 	'implementer': '0x41',
+	'flags': [
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'part_number': '0xd08',
 	'numa': false
 }