diff mbox series

net/mlx5: add wire vport hint

Message ID 1605281572-31195-1-git-send-email-viacheslavo@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: add wire vport hint |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/iol-mellanox-Performance success Performance Testing PASS
ci/Intel-compilation success Compilation OK

Commit Message

Slava Ovsiienko Nov. 13, 2020, 3:32 p.m. UTC 
  The kernel can use two approaches to distinguish the E-Switch
source vport in the packet metadata - either with dedicated
source_port field or register C0. To eliminate the extra source
vport matching in the hardware the source_port field can be
set to specific values (0xFFFF) for the wire source port.

This match can be applied to recognize wire port only in FDB
domain. Missing the register C0 match in the NIC Rx domain causes
incorrect representor steering within shared IB device ports
and must be always specified (if kernel uses this approach).

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 39 +++++++++++++++++++++++++++++----------
 1 file changed, 29 insertions(+), 10 deletions(-)

Comments

Raslan Darawsheh Nov. 17, 2020, 4:18 p.m. UTC | #1 
Hi,

> -----Original Message-----
> From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Sent: Friday, November 13, 2020 5:33 PM
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Matan Azrad
> <matan@nvidia.com>
> Subject: [PATCH] net/mlx5: add wire vport hint
> 
> The kernel can use two approaches to distinguish the E-Switch
> source vport in the packet metadata - either with dedicated
> source_port field or register C0. To eliminate the extra source
> vport matching in the hardware the source_port field can be
> set to specific values (0xFFFF) for the wire source port.
> 
> This match can be applied to recognize wire port only in FDB
> domain. Missing the register C0 match in the NIC Rx domain causes
> incorrect representor steering within shared IB device ports
> and must be always specified (if kernel uses this approach).
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---
>  drivers/net/mlx5/mlx5_flow_dv.c | 39
> +++++++++++++++++++++++++++++----------
>  1 file changed, 29 insertions(+), 10 deletions(-)

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 78c710f..e31bdac 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7596,13 +7596,16 @@  struct mlx5_hlist_entry *
  *   Flow matcher value.
  * @param[in] item
  *   Flow pattern to translate.
+ * @param[in]
+ *   Flow attributes.
  *
  * @return
  *   0 on success, a negative errno value otherwise.
  */
 static int
 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
-			       void *key, const struct rte_flow_item *item)
+			       void *key, const struct rte_flow_item *item,
+			       const struct rte_flow_attr *attr)
 {
 	const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
 	const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
@@ -7614,14 +7617,30 @@  struct mlx5_hlist_entry *
 	priv = mlx5_port_to_eswitch_info(id, item == NULL);
 	if (!priv)
 		return -rte_errno;
-	/* Translate to vport field or to metadata, depending on mode. */
-	if (priv->vport_meta_mask)
-		flow_dv_translate_item_meta_vport(matcher, key,
-						  priv->vport_meta_tag,
-						  priv->vport_meta_mask);
-	else
+	/*
+	 * Translate to vport field or to metadata, depending on mode.
+	 * Kernel can use either misc.source_port or half of C0 metadata
+	 * register.
+	 */
+	if (priv->vport_meta_mask) {
+		/*
+		 * Provide the hint for SW steering library
+		 * to insert the flow into ingress domain and
+		 * save the extra vport match.
+		 */
+		if (mask == 0xffff && priv->vport_id == 0xffff &&
+		    priv->pf_bond < 0 && attr->transfer)
+			flow_dv_translate_item_source_vport
+				(matcher, key, priv->vport_id, mask);
+		else
+			flow_dv_translate_item_meta_vport
+				(matcher, key,
+				 priv->vport_meta_tag,
+				 priv->vport_meta_mask);
+	} else {
 		flow_dv_translate_item_source_vport(matcher, key,
 						    priv->vport_id, mask);
+	}
 	return 0;
 }
 
@@ -10218,8 +10237,8 @@  struct mlx5_cache_entry *
 						  NULL, "item not supported");
 		switch (item_type) {
 		case RTE_FLOW_ITEM_TYPE_PORT_ID:
-			flow_dv_translate_item_port_id(dev, match_mask,
-						       match_value, items);
+			flow_dv_translate_item_port_id
+				(dev, match_mask, match_value, items, attr);
 			last_item = MLX5_FLOW_ITEM_PORT_ID;
 			break;
 		case RTE_FLOW_ITEM_TYPE_ETH:
@@ -10445,7 +10464,7 @@  struct mlx5_cache_entry *
 	if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
 	    (priv->representor || priv->master)) {
 		if (flow_dv_translate_item_port_id(dev, match_mask,
-						   match_value, NULL))
+						   match_value, NULL, attr))
 			return -rte_errno;
 	}
 #ifdef RTE_LIBRTE_MLX5_DEBUG