[2/2] vdpa/mlx5: hardware queue moderation

Message ID 1609902390-3453-2-git-send-email-xuemingl@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Maxime Coquelin
Headers
Series [1/2] common/mlx5: support vDPA completion queue moderation |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-abi-testing success Testing PASS
ci/iol-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/Intel-compilation success Compilation OK

Commit Message

Xueming Li Jan. 6, 2021, 3:06 a.m. UTC
  The next parameters control the HW queue moderation feature.
This feature helps to control the traffic performance and latency
tradeoff.

Each packet completion report from HW to SW requires CQ processing by SW
and triggers interrupt for the guest driver. Interrupt report and
handling cost CPU cycles and time and the amount of this affects
directly on packet performance and latency.

hw_latency_mode parameters [int]
  0, HW default.
  1, Latency is counted from the first packet completion report.
  2, Latency is counted from the last packet completion.
hw_max_latency_us parameters [int]
  0 - 4095, The maximum time in microseconds that packet completion
report can be delayed.
hw_max_pending_comp parameter [int]
  0 - 65535, The maximum number of pending packets completions in an HW
queue.

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
---
 doc/guides/vdpadevs/mlx5.rst        | 24 ++++++++++++++++++++++++
 drivers/vdpa/mlx5/mlx5_vdpa.c       |  6 ++++++
 drivers/vdpa/mlx5/mlx5_vdpa.h       |  3 +++
 drivers/vdpa/mlx5/mlx5_vdpa_virtq.c |  3 +++
 4 files changed, 36 insertions(+)
  

Comments

Maxime Coquelin Jan. 7, 2021, 5:38 p.m. UTC | #1
On 1/6/21 4:06 AM, Xueming Li wrote:
> The next parameters control the HW queue moderation feature.
> This feature helps to control the traffic performance and latency
> tradeoff.
> 
> Each packet completion report from HW to SW requires CQ processing by SW
> and triggers interrupt for the guest driver. Interrupt report and
> handling cost CPU cycles and time and the amount of this affects
> directly on packet performance and latency.
> 
> hw_latency_mode parameters [int]
>   0, HW default.
>   1, Latency is counted from the first packet completion report.
>   2, Latency is counted from the last packet completion.
> hw_max_latency_us parameters [int]
>   0 - 4095, The maximum time in microseconds that packet completion
> report can be delayed.
> hw_max_pending_comp parameter [int]
>   0 - 65535, The maximum number of pending packets completions in an HW
> queue.
> 
> Signed-off-by: Xueming Li <xuemingl@nvidia.com>
> ---
>  doc/guides/vdpadevs/mlx5.rst        | 24 ++++++++++++++++++++++++
>  drivers/vdpa/mlx5/mlx5_vdpa.c       |  6 ++++++
>  drivers/vdpa/mlx5/mlx5_vdpa.h       |  3 +++
>  drivers/vdpa/mlx5/mlx5_vdpa_virtq.c |  3 +++
>  4 files changed, 36 insertions(+)

Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

Thanks,
Maxime
  
Maxime Coquelin Jan. 8, 2021, 9:17 a.m. UTC | #2
On 1/6/21 4:06 AM, Xueming Li wrote:
> The next parameters control the HW queue moderation feature.
> This feature helps to control the traffic performance and latency
> tradeoff.
> 
> Each packet completion report from HW to SW requires CQ processing by SW
> and triggers interrupt for the guest driver. Interrupt report and
> handling cost CPU cycles and time and the amount of this affects
> directly on packet performance and latency.
> 
> hw_latency_mode parameters [int]
>   0, HW default.
>   1, Latency is counted from the first packet completion report.
>   2, Latency is counted from the last packet completion.
> hw_max_latency_us parameters [int]
>   0 - 4095, The maximum time in microseconds that packet completion
> report can be delayed.
> hw_max_pending_comp parameter [int]
>   0 - 65535, The maximum number of pending packets completions in an HW
> queue.
> 
> Signed-off-by: Xueming Li <xuemingl@nvidia.com>
> ---
>  doc/guides/vdpadevs/mlx5.rst        | 24 ++++++++++++++++++++++++
>  drivers/vdpa/mlx5/mlx5_vdpa.c       |  6 ++++++
>  drivers/vdpa/mlx5/mlx5_vdpa.h       |  3 +++
>  drivers/vdpa/mlx5/mlx5_vdpa_virtq.c |  3 +++
>  4 files changed, 36 insertions(+)

Series applied to dpdk-next-virtio/main.

Thanks,
Maxime
  

Patch

diff --git a/doc/guides/vdpadevs/mlx5.rst b/doc/guides/vdpadevs/mlx5.rst
index 3a6d88362d..587652b3ae 100644
--- a/doc/guides/vdpadevs/mlx5.rst
+++ b/doc/guides/vdpadevs/mlx5.rst
@@ -135,6 +135,30 @@  Driver options
   interrupts are configured to the device in order to notify traffic for the
   driver. Default value is 2s.
 
+- ``hw_latency_mode`` parameter [int]
+
+  The completion queue moderation mode:
+
+  - 0, HW default.
+
+  - 1, Latency is counted from the first packet completion report.
+
+  - 2, Latency is counted from the last packet completion.
+
+- ``hw_max_latency_us`` parameter [int]
+
+  - 1 - 4095, The maximum time in microseconds that packet completion report
+    can be delayed.
+
+  - 0, HW default.
+
+- ``hw_max_pending_comp`` parameter [int]
+
+  - 1 - 65535, The maximum number of pending packets completions in an HW queue.
+
+  - 0, HW default.
+
+
 Error handling
 ^^^^^^^^^^^^^^
 
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c
index b64f364eb7..bb9477cc52 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa.c
+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c
@@ -630,6 +630,12 @@  mlx5_vdpa_args_check_handler(const char *key, const char *val, void *opaque)
 		priv->event_us = (uint32_t)tmp;
 	} else if (strcmp(key, "no_traffic_time") == 0) {
 		priv->no_traffic_time_s = (uint32_t)tmp;
+	} else if (strcmp(key, "hw_latency_mode") == 0) {
+		priv->hw_latency_mode = (uint32_t)tmp;
+	} else if (strcmp(key, "hw_max_latency_us") == 0) {
+		priv->hw_max_latency_us = (uint32_t)tmp;
+	} else if (strcmp(key, "hw_max_pending_comp") == 0) {
+		priv->hw_max_pending_comp = (uint32_t)tmp;
 	} else {
 		DRV_LOG(WARNING, "Invalid key %s.", key);
 	}
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h
index d039ada65b..9d2d9c1cd5 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa.h
+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h
@@ -134,6 +134,9 @@  struct mlx5_vdpa_priv {
 	uint32_t event_us;
 	uint32_t timer_delay_us;
 	uint32_t no_traffic_time_s;
+	uint8_t hw_latency_mode; /* Hardware CQ moderation mode. */
+	uint16_t hw_max_latency_us; /* Hardware CQ moderation period in usec. */
+	uint16_t hw_max_pending_comp; /* Hardware CQ moderation counter. */
 	struct rte_vdpa_device *vdev; /* vDPA device. */
 	int vid; /* vhost device id. */
 	struct ibv_context *ctx; /* Device context. */
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c
index 3e882e4000..332753fd62 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c
+++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c
@@ -327,6 +327,9 @@  mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index)
 	attr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id;
 	attr.queue_index = index;
 	attr.pd = priv->pdn;
+	attr.hw_latency_mode = priv->hw_latency_mode;
+	attr.hw_max_latency_us = priv->hw_max_latency_us;
+	attr.hw_max_pending_comp = priv->hw_max_pending_comp;
 	virtq->virtq = mlx5_devx_cmd_create_virtq(priv->ctx, &attr);
 	virtq->priv = priv;
 	if (!virtq->virtq)