From patchwork Thu May 6 09:29:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "humin (Q)" X-Patchwork-Id: 92995 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 34624A0524; Thu, 6 May 2021 11:29:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A44D3410EE; Thu, 6 May 2021 11:29:42 +0200 (CEST) Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) by mails.dpdk.org (Postfix) with ESMTP id 443DC410DB for ; Thu, 6 May 2021 11:29:41 +0200 (CEST) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FbSsb0mhPzkkgc; Thu, 6 May 2021 17:27:31 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Thu, 6 May 2021 17:29:33 +0800 From: "Min Hu (Connor)" To: CC: , , , , Date: Thu, 6 May 2021 17:29:36 +0800 Message-ID: <1620293376-41815-1-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618470748-12369-1-git-send-email-humin29@huawei.com> References: <1618470748-12369-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2] examples/timer: fix incorrect time interval X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chengchang Tang Timer sample example assumes that the frequency of the timer is about 2Ghz to control the period of calling rte_timer_manage(). But this assumption is easy to fail. For example. the frequency of tsc on ARM64 is much less than 2Ghz. This patch uses the frequency of the current timer to calculate the correct time interval to ensure consistent result on all platforms. In addition, the rte_rdtsc() is replaced with the more recommended rte_get_timer_cycles function in this patch. Fixes: af75078fece3 ("first public release") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- v2: * delete confusing comments. --- examples/timer/main.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/examples/timer/main.c b/examples/timer/main.c index d67301e..d270ce4 100644 --- a/examples/timer/main.c +++ b/examples/timer/main.c @@ -18,8 +18,7 @@ #include #include -#define TIMER_RESOLUTION_CYCLES 20000000ULL /* around 10ms at 2 Ghz */ - +static uint64_t timer_resolution_cycles; static struct rte_timer timer0; static struct rte_timer timer1; @@ -66,15 +65,14 @@ lcore_mainloop(__rte_unused void *arg) while (1) { /* - * Call the timer handler on each core: as we don't - * need a very precise timer, so only call - * rte_timer_manage() every ~10ms (at 2Ghz). In a real - * application, this will enhance performances as - * reading the HPET timer is not efficient. + * Call the timer handler on each core: as we don't need a + * very precise timer, so only call rte_timer_manage() + * every ~10ms. In a real application, this will enhance + * performances as reading the HPET timer is not efficient. */ - cur_tsc = rte_rdtsc(); + cur_tsc = rte_get_timer_cycles(); diff_tsc = cur_tsc - prev_tsc; - if (diff_tsc > TIMER_RESOLUTION_CYCLES) { + if (diff_tsc > timer_resolution_cycles) { rte_timer_manage(); prev_tsc = cur_tsc; } @@ -100,8 +98,10 @@ main(int argc, char **argv) rte_timer_init(&timer0); rte_timer_init(&timer1); - /* load timer0, every second, on main lcore, reloaded automatically */ hz = rte_get_timer_hz(); + timer_resolution_cycles = hz * 10 / 1000; /* around 10ms */ + + /* load timer0, every second, on main lcore, reloaded automatically */ lcore_id = rte_lcore_id(); rte_timer_reset(&timer0, hz, PERIODICAL, lcore_id, timer0_cb, NULL);