[v3,2/8] common/cnxk: support SMQ flush

Message ID 1632291108-28780-3-git-send-email-skoteshwar@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series Add TM Support for CN9K and CN10K |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Satha Koteswara Rao Kottidi Sept. 22, 2021, 6:11 a.m. UTC
  From: Satha Rao <skoteshwar@marvell.com>

Each NIX interface had one or more SMQs connected to SQs to send
packets. When flush enabled on SMQ, hardware will push all packets
from SMQ to physical link. This API will enable flush on all SMQs
of an interface.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/hw/nix.h         |  6 ++++
 drivers/common/cnxk/roc_nix.h        |  1 +
 drivers/common/cnxk/roc_nix_tm_ops.c | 50 ++++++++++++++++++++++++++++
 drivers/common/cnxk/version.map      |  1 +
 4 files changed, 58 insertions(+)
  

Patch

diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index a0ffd25660..bc908c25b1 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -2189,4 +2189,10 @@  struct nix_lso_format {
 #define NIX_LSO_FORMAT_IDX_TSOV4 0
 #define NIX_LSO_FORMAT_IDX_TSOV6 1
 
+/* [CN10K, .) */
+#define NIX_SENDSTATALG_MASK	  0x7
+#define NIX_SENDSTATALG_SEL_MASK  0x8
+#define NIX_SENDSTAT_IOFFSET_MASK 0xFFF
+#define NIX_SENDSTAT_OOFFSET_MASK 0xFFF
+
 #endif /* __NIX_HW_H__ */
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index b0e6fabe31..ac7bd7e3ec 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -468,6 +468,7 @@  int __roc_api roc_nix_tm_rsrc_count(struct roc_nix *roc_nix,
 int __roc_api roc_nix_tm_node_name_get(struct roc_nix *roc_nix,
 				       uint32_t node_id, char *buf,
 				       size_t buflen);
+int __roc_api roc_nix_smq_flush(struct roc_nix *roc_nix);
 
 /* MAC */
 int __roc_api roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start);
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index f2173c9a58..02ee08bc4c 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -317,6 +317,56 @@  roc_nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id, bool free)
 	return nix_tm_node_delete(roc_nix, node_id, ROC_NIX_TM_USER, free);
 }
 
+int
+roc_nix_smq_flush(struct roc_nix *roc_nix)
+{
+	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	struct nix_tm_node_list *list;
+	enum roc_nix_tm_tree tree;
+	struct nix_tm_node *node;
+	int rc = 0;
+
+	if (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))
+		return 0;
+
+	tree = nix->tm_tree;
+	list = nix_tm_node_list(nix, tree);
+
+	/* XOFF & Flush all SMQ's. HRM mandates
+	 * all SQ's empty before SMQ flush is issued.
+	 */
+	TAILQ_FOREACH(node, list, node) {
+		if (node->hw_lvl != NIX_TXSCH_LVL_SMQ)
+			continue;
+		if (!(node->flags & NIX_TM_NODE_HWRES))
+			continue;
+
+		rc = nix_tm_smq_xoff(nix, node, true);
+		if (rc) {
+			plt_err("Failed to enable smq %u, rc=%d", node->hw_id,
+				rc);
+			goto exit;
+		}
+	}
+
+	/* XON all SMQ's */
+	TAILQ_FOREACH(node, list, node) {
+		if (node->hw_lvl != NIX_TXSCH_LVL_SMQ)
+			continue;
+		if (!(node->flags & NIX_TM_NODE_HWRES))
+			continue;
+
+		rc = nix_tm_smq_xoff(nix, node, false);
+		if (rc) {
+			plt_err("Failed to enable smq %u, rc=%d", node->hw_id,
+				rc);
+			goto exit;
+		}
+	}
+exit:
+	return rc;
+}
+
 int
 roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix)
 {
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 5df2e56ce6..388f9385e0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -170,6 +170,7 @@  INTERNAL {
 	roc_nix_xstats_names_get;
 	roc_nix_switch_hdr_set;
 	roc_nix_eeprom_info_get;
+	roc_nix_smq_flush;
 	roc_nix_tm_dump;
 	roc_nix_tm_fini;
 	roc_nix_tm_free_resources;