From patchwork Tue Dec 7 06:50:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 104959 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9636FA034F; Tue, 7 Dec 2021 07:51:16 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2EFAC40140; Tue, 7 Dec 2021 07:51:16 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0C4DA40040 for ; Tue, 7 Dec 2021 07:51:13 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1B75a07E014960 for ; Mon, 6 Dec 2021 22:51:13 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6FZxWCUzgMmhUJb8YOGRH/TkH+Q1tuMI1WmoB3lB3pw=; b=hNnqZPGqkjxUzh6Uo0A1p/OFfMYVz5osSRLHB/3WyiNLeLUm6KnnOliHl4r5BasLfx8Y paEtGe+20TSvF4yaB8XnuU67uIZFahQO27Nv7YP+Xw1u3258IMJvp1y71+zgli6BbrRs c4DVjrhXbU5XrcyynJb13wXfpf2lhRqdGxPgtPJ4+9+lQAIXwbccZGMWEHUhWOuLeoDl gRqBs26Yv74i5aDKGsG2xnIpx8tt2Xj2uXZ3Rf3JCk+kQAaejY2sCsy6n0oUQnb3JNp5 twd/u9gFbstYBdHXnXXlDB6kngo+mRC2aLGlboNhOwJBejzyt1Pm3+3fP5l9XcCrvfAH CA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ct1hyg7c7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 06 Dec 2021 22:51:13 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 6 Dec 2021 22:51:10 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Dec 2021 22:51:10 -0800 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 299FE3F7071; Mon, 6 Dec 2021 22:51:06 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Anoob Joseph , Archana Muniganti , Tejasree Kondoj , , Aakash Sasidharan Subject: [PATCH 01/25] common/cnxk: define minor opcodes for MISC opcode Date: Tue, 7 Dec 2021 12:20:34 +0530 Message-ID: <1638859858-734-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1638859858-734-1-git-send-email-anoobj@marvell.com> References: <1638859858-734-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: qM517bsjkO2j38w_8AXWQbqH5ukxU71a X-Proofpoint-GUID: qM517bsjkO2j38w_8AXWQbqH5ukxU71a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-07_02,2021-12-06_02,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MISC CPT instruction behaves differently based on minor opcode. Define the missing minor opcodes for MISC major opcode. Signed-off-by: Aakash Sasidharan Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_se.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index 5be832f..253575a 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -15,7 +15,11 @@ #define ROC_SE_MAJOR_OP_HMAC 0x35 #define ROC_SE_MAJOR_OP_ZUC_SNOW3G 0x37 #define ROC_SE_MAJOR_OP_KASUMI 0x38 -#define ROC_SE_MAJOR_OP_MISC 0x01 + +#define ROC_SE_MAJOR_OP_MISC 0x01 +#define ROC_SE_MISC_MINOR_OP_PASSTHROUGH 0x03 +#define ROC_SE_MISC_MINOR_OP_DUMMY 0x04 +#define ROC_SE_MISC_MINOR_OP_HW_SUPPORT 0x08 #define ROC_SE_MAX_AAD_SIZE 64 #define ROC_SE_MAX_MAC_LEN 64