From patchwork Tue Dec 7 06:50:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 104974 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CC107A034F; Tue, 7 Dec 2021 07:52:51 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A12EE4275C; Tue, 7 Dec 2021 07:52:12 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 00CFE42748 for ; Tue, 7 Dec 2021 07:52:08 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1B76pJvt018306 for ; Mon, 6 Dec 2021 22:52:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=82vfpzglZCyiv3FHCDO8TCYIavngPcI7B+XzQQ3JqaI=; b=i5Y1nELPgaiHf6eLybB1LZAttVig1PA49pjtTDu0wAxJ6fdlEhOYjCUgIMQWH3Tg/Qd0 soXixnvOxjXtJNp0LlyoOuF8W9m0+9hY9SJ9l9gJAlDRLFvaaJi2jvIlcyNg0mJxNz0f PWzxpMZjcSx6eA13WJVDwRC/vfuzI2QUeQAL/7M3rpQ1lemf7RCKWEE4VWGeSa9g3xtZ +teq8DVsF1581FciDJBx6TTc2p2lGANUwPeH8tYqNNvxfkK7dh+Wuadero66ayYE+Czv kggmNgbZpHvNR4zA9D37LIulW2obH6H9qwcTnuOTLalXW8jm/2x1mpey+8Jxzg33LN68 /Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ct2q9004x-10 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 06 Dec 2021 22:52:08 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 6 Dec 2021 22:51:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 6 Dec 2021 22:51:28 -0800 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 548A83F7071; Mon, 6 Dec 2021 22:51:26 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Shijith Thotton , Archana Muniganti , Tejasree Kondoj , Subject: [PATCH 06/25] crypto/cnxk: only enable queues that are allocated Date: Tue, 7 Dec 2021 12:20:39 +0530 Message-ID: <1638859858-734-7-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1638859858-734-1-git-send-email-anoobj@marvell.com> References: <1638859858-734-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: YrjTQIjAe1PXty3N-ABrkSCFiDh0CWaT X-Proofpoint-ORIG-GUID: YrjTQIjAe1PXty3N-ABrkSCFiDh0CWaT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-07_02,2021-12-06_02,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shijith Thotton Only enable/disable queue pairs that are allocated during cryptodev start/stop. Fixes: 6a95dbc1a291 ("crypto/cnxk: add dev start and dev stop") Signed-off-by: Shijith Thotton --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index a2281fb..21ee09f 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -100,8 +100,13 @@ cnxk_cpt_dev_start(struct rte_cryptodev *dev) uint16_t nb_lf = roc_cpt->nb_lf; uint16_t qp_id; - for (qp_id = 0; qp_id < nb_lf; qp_id++) + for (qp_id = 0; qp_id < nb_lf; qp_id++) { + /* Application may not setup all queue pair */ + if (roc_cpt->lf[qp_id] == NULL) + continue; + roc_cpt_iq_enable(roc_cpt->lf[qp_id]); + } return 0; } @@ -114,8 +119,12 @@ cnxk_cpt_dev_stop(struct rte_cryptodev *dev) uint16_t nb_lf = roc_cpt->nb_lf; uint16_t qp_id; - for (qp_id = 0; qp_id < nb_lf; qp_id++) + for (qp_id = 0; qp_id < nb_lf; qp_id++) { + if (roc_cpt->lf[qp_id] == NULL) + continue; + roc_cpt_iq_disable(roc_cpt->lf[qp_id]); + } } int