From patchwork Fri Dec 17 09:19:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 105203 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FD6FA0352; Fri, 17 Dec 2021 10:20:36 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4C30840F35; Fri, 17 Dec 2021 10:20:35 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id EEB7C40F35 for ; Fri, 17 Dec 2021 10:20:33 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BH3fMFZ015144 for ; Fri, 17 Dec 2021 01:20:33 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6FZxWCUzgMmhUJb8YOGRH/TkH+Q1tuMI1WmoB3lB3pw=; b=P23vS9e+UyBp56dzFfgbdjC6jRpj392QUR327fDSskLo8XHhBcZsJ+UZRmwoqz97Xe0E jDP8U5zM54ObWByrLcMeTj3vmmzQpXPVO1xhNDhPT4CiWbMd7yPjnOhOiSgSTUtW1VlB DNzpyiu5QbyPhYt2uA0O/BCDzSTjbQADvNdvvzS3TTOhMtDrUs2w+VkF69nUyjYzlR4H 9hlPdanvtFPp8gvVOxxbya0JS3MIfEYdt+iT30v19etAFisfvgL/8qe1/mgSGfwnCF4U PQsih0bFb78qSgnXuSodKpKm76Ie01z7PmolnKRAlCQ4layBVcZ9cMO7al+4HLIfsgiD pQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3d0b372t8k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 17 Dec 2021 01:20:33 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 17 Dec 2021 01:20:31 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 17 Dec 2021 01:20:31 -0800 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id BDD4E3F70A3; Fri, 17 Dec 2021 01:20:28 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Anoob Joseph , Archana Muniganti , Tejasree Kondoj , , Aakash Sasidharan Subject: [PATCH v3 01/29] common/cnxk: define minor opcodes for MISC opcode Date: Fri, 17 Dec 2021 14:49:43 +0530 Message-ID: <1639732811-1440-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1639732811-1440-1-git-send-email-anoobj@marvell.com> References: <1639676975-1316-1-git-send-email-anoobj@marvell.com> <1639732811-1440-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NUyEjzZHuYIlSp4z44FURfursNP4LezR X-Proofpoint-GUID: NUyEjzZHuYIlSp4z44FURfursNP4LezR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-17_03,2021-12-16_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MISC CPT instruction behaves differently based on minor opcode. Define the missing minor opcodes for MISC major opcode. Signed-off-by: Aakash Sasidharan Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_se.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index 5be832f..253575a 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -15,7 +15,11 @@ #define ROC_SE_MAJOR_OP_HMAC 0x35 #define ROC_SE_MAJOR_OP_ZUC_SNOW3G 0x37 #define ROC_SE_MAJOR_OP_KASUMI 0x38 -#define ROC_SE_MAJOR_OP_MISC 0x01 + +#define ROC_SE_MAJOR_OP_MISC 0x01 +#define ROC_SE_MISC_MINOR_OP_PASSTHROUGH 0x03 +#define ROC_SE_MISC_MINOR_OP_DUMMY 0x04 +#define ROC_SE_MISC_MINOR_OP_HW_SUPPORT 0x08 #define ROC_SE_MAX_AAD_SIZE 64 #define ROC_SE_MAX_MAC_LEN 64