@@ -65,6 +65,18 @@
#define ACC100_QOS_GBR 0
#endif
+#ifdef RTE_BASEBAND_ACC101
+#include <rte_acc101_cfg.h>
+#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
+#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
+#define ACC101_QMGR_NUM_AQS 16
+#define ACC101_QMGR_NUM_QGS 2
+#define ACC101_QMGR_AQ_DEPTH 5
+#define ACC101_QMGR_INVALID_IDX -1
+#define ACC101_QMGR_RR 1
+#define ACC101_QOS_GBR 0
+#endif
+
#define OPS_CACHE_SIZE 256U
#define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */
@@ -766,6 +778,63 @@ typedef int (test_case_function)(struct active_device *ad,
info->dev_name);
}
#endif
+#ifdef RTE_BASEBAND_ACC101
+ if ((get_init_device() == true) &&
+ (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME))) {
+ struct rte_acc101_conf conf;
+ unsigned int i;
+
+ printf("Configure ACC101 FEC Driver %s with default values\n",
+ info->drv.driver_name);
+
+ /* clear default configuration before initialization */
+ memset(&conf, 0, sizeof(struct rte_acc101_conf));
+
+ /* Always set in PF mode for built-in configuration */
+ conf.pf_mode_en = true;
+ for (i = 0; i < RTE_ACC101_NUM_VFS; ++i) {
+ conf.arb_dl_4g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_dl_4g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_dl_4g[i].round_robin_weight = ACC101_QMGR_RR;
+ conf.arb_ul_4g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_ul_4g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_ul_4g[i].round_robin_weight = ACC101_QMGR_RR;
+ conf.arb_dl_5g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_dl_5g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_dl_5g[i].round_robin_weight = ACC101_QMGR_RR;
+ conf.arb_ul_5g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_ul_5g[i].gbr_threshold1 = ACC101_QOS_GBR;
+ conf.arb_ul_5g[i].round_robin_weight = ACC101_QMGR_RR;
+ }
+
+ conf.input_pos_llr_1_bit = true;
+ conf.output_pos_llr_1_bit = true;
+ conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */
+
+ conf.q_ul_4g.num_qgroups = ACC101_QMGR_NUM_QGS;
+ conf.q_ul_4g.first_qgroup_index = ACC101_QMGR_INVALID_IDX;
+ conf.q_ul_4g.num_aqs_per_groups = ACC101_QMGR_NUM_AQS;
+ conf.q_ul_4g.aq_depth_log2 = ACC101_QMGR_AQ_DEPTH;
+ conf.q_dl_4g.num_qgroups = ACC101_QMGR_NUM_QGS;
+ conf.q_dl_4g.first_qgroup_index = ACC101_QMGR_INVALID_IDX;
+ conf.q_dl_4g.num_aqs_per_groups = ACC101_QMGR_NUM_AQS;
+ conf.q_dl_4g.aq_depth_log2 = ACC101_QMGR_AQ_DEPTH;
+ conf.q_ul_5g.num_qgroups = ACC101_QMGR_NUM_QGS;
+ conf.q_ul_5g.first_qgroup_index = ACC101_QMGR_INVALID_IDX;
+ conf.q_ul_5g.num_aqs_per_groups = ACC101_QMGR_NUM_AQS;
+ conf.q_ul_5g.aq_depth_log2 = ACC101_QMGR_AQ_DEPTH;
+ conf.q_dl_5g.num_qgroups = ACC101_QMGR_NUM_QGS;
+ conf.q_dl_5g.first_qgroup_index = ACC101_QMGR_INVALID_IDX;
+ conf.q_dl_5g.num_aqs_per_groups = ACC101_QMGR_NUM_AQS;
+ conf.q_dl_5g.aq_depth_log2 = ACC101_QMGR_AQ_DEPTH;
+
+ /* setup PF with configuration information */
+ ret = rte_acc101_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC101 PF for bbdev %s",
+ info->dev_name);
+ }
+#endif
/* Let's refresh this now this is configured */
rte_bbdev_info_get(dev_id, info);
nb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues);
@@ -55,6 +55,10 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Added Intel ACC101 baseband PMD.**
+
+ * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
+ * See the :doc:`../bbdevs/acc101` for more details.
Removed Items
-------------
@@ -4,3 +4,5 @@
deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']
sources = files('rte_acc101_pmd.c')
+
+headers = files('rte_acc101_cfg.h')
@@ -89,6 +89,23 @@ struct rte_acc101_conf {
struct rte_acc101_arbitration arb_dl_5g[RTE_ACC101_NUM_VFS];
};
+/**
+ * Configure a ACC101 device
+ *
+ * @param dev_name
+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ * It can also be retrieved for a bbdev device from the dev_name field in the
+ * rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ * Configuration to apply to ACC101 HW.
+ *
+ * @return
+ * Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc101_conf *conf);
+
#ifdef __cplusplus
}
#endif
@@ -84,6 +84,26 @@
enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, NUM_ACC};
+/* Return the accelerator enum for a Queue Group Index */
+static inline int
+accFromQgid(int qg_idx, const struct rte_acc101_conf *acc101_conf)
+{
+ int accQg[ACC101_NUM_QGRPS];
+ int NumQGroupsPerFn[NUM_ACC];
+ int acc, qgIdx, qgIndex = 0;
+ for (qgIdx = 0; qgIdx < ACC101_NUM_QGRPS; qgIdx++)
+ accQg[qgIdx] = 0;
+ NumQGroupsPerFn[UL_4G] = acc101_conf->q_ul_4g.num_qgroups;
+ NumQGroupsPerFn[UL_5G] = acc101_conf->q_ul_5g.num_qgroups;
+ NumQGroupsPerFn[DL_4G] = acc101_conf->q_dl_4g.num_qgroups;
+ NumQGroupsPerFn[DL_5G] = acc101_conf->q_dl_5g.num_qgroups;
+ for (acc = UL_4G; acc < NUM_ACC; acc++)
+ for (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)
+ accQg[qgIndex++] = acc;
+ acc = accQg[qg_idx];
+ return acc;
+}
+
/* Return the queue topology for a Queue Group Index */
static inline void
qtopFromAcc(struct rte_acc101_queue_topology **qtop, int acc_enum,
@@ -112,6 +132,30 @@
*qtop = p_qtop;
}
+/* Return the AQ depth for a Queue Group Index */
+static inline int
+aqDepth(int qg_idx, struct rte_acc101_conf *acc101_conf)
+{
+ struct rte_acc101_queue_topology *q_top = NULL;
+ int acc_enum = accFromQgid(qg_idx, acc101_conf);
+ qtopFromAcc(&q_top, acc_enum, acc101_conf);
+ if (unlikely(q_top == NULL))
+ return 1;
+ return q_top->aq_depth_log2;
+}
+
+/* Return the AQ depth for a Queue Group Index */
+static inline int
+aqNum(int qg_idx, struct rte_acc101_conf *acc101_conf)
+{
+ struct rte_acc101_queue_topology *q_top = NULL;
+ int acc_enum = accFromQgid(qg_idx, acc101_conf);
+ qtopFromAcc(&q_top, acc_enum, acc101_conf);
+ if (unlikely(q_top == NULL))
+ return 0;
+ return q_top->num_aqs_per_groups;
+}
+
static void
initQTop(struct rte_acc101_conf *acc101_conf)
{
@@ -4120,3 +4164,294 @@ static int acc101_pci_remove(struct rte_pci_device *pci_dev)
RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);
RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);
RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);
+
+/* Initial configuration of a ACC101 device prior to running configure() */
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc101_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc101_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc101_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc101_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc101_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc101_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc101_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc101_conf, conf, sizeof(d->acc101_conf));
+
+ /* PCIe Bridge configuration */
+ acc101_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
+ for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
+ acc101_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
+
+ /* Prevent blocking AXI read on BRESP for AXI Write */
+ address = HwPfPcieGpexAxiPioControl;
+ value = ACC101_CFG_PCI_AXI;
+ acc101_reg_write(d, address, value);
+
+ /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
+ usleep(2000);
+ acc101_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* Set the default 5GDL DMA configuration */
+ acc101_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
+
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC101_CLOCK_GATING_EN;
+ acc101_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc101_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC101_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc101_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC101_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc101_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc101_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc101_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ address = HWPfDmaConfig1Reg;
+ int alen_r = 0xF;
+ int alen_w = 0x7;
+ value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
+ acc101_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc101_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc101_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc101_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_0;
+ acc101_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_1;
+ acc101_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_2;
+ acc101_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_3;
+ acc101_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC101_CFG_QMGR_HI_P;
+ acc101_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc101_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_4G;
+ template_idx <= ACC101_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc101_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_5G;
+ template_idx <= ACC101_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg +
+ ACC101_ENGINE_OFFSET * template_idx;
+ status = (acc101_reg_read(d, address) >> 4) & 0xF;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc101_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc101_reg_write(d, address, 0);
+ }
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_4G;
+ template_idx <= ACC101_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc101_reg_write(d, address, value);
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_5G;
+ template_idx <= ACC101_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc101_reg_write(d, address, value);
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ address = HWPfQmgrGrpFunction0;
+ value = 0;
+ for (qg_idx = 0; qg_idx < 8; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc]<<(qg_idx * 4);
+ }
+ acc101_reg_write(d, address, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc101_reg_write(d, address, value);
+ }
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC101_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc101_reg_write(d, address, value);
+ }
+ }
+
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC101_BYTES_IN_WORD + qg_idx
+ * ACC101_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc101_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC101_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ acc101_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc101_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc101_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc101_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc101_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc101_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
+ acc101_reg_write(d, address, value);
+ /* Explicitly releasing AXI after PF Mode and 2 ms */
+ usleep(2000);
+ acc101_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc101_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc101_reg_write(d, address, value);
+
+ /* HARQ DDR Configuration */
+ unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfDmaVfDdrBaseRw + vf_idx
+ * 0x10;
+ value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
+ (ddrSizeInMb - 1);
+ acc101_reg_write(d, address, value);
+ }
+ usleep(ACC101_LONG_WAIT);
+
+ rte_bbdev_log_debug("PF ACC101 configuration complete for %s", dev_name);
+ return 0;
+}
@@ -31,6 +31,11 @@
#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
+/* Define as 1 to use only a single FEC engine */
+#ifndef RTE_ACC101_SINGLE_FEC
+#define RTE_ACC101_SINGLE_FEC 0
+#endif
+
/* Values used in filling in descriptors */
#define ACC101_DMA_DESC_TYPE 2
#define ACC101_DMA_CODE_BLK_MODE 0
@@ -79,10 +84,25 @@
#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
+#define ACC101_TMPL_PRI_0 0x03020100
+#define ACC101_TMPL_PRI_1 0x07060504
+#define ACC101_TMPL_PRI_2 0x0b0a0908
+#define ACC101_TMPL_PRI_3 0x0f0e0d0c
#define ACC101_QUEUE_ENABLE 0x80000000 /* Bit to mark Queue as Enabled */
+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
#define ACC101_FDONE 0x80000000
#define ACC101_SDONE 0x40000000
+#define ACC101_NUM_TMPL 32
+/* Mapping of signals for the available engines */
+#define ACC101_SIG_UL_5G 0
+#define ACC101_SIG_UL_5G_LAST 8
+#define ACC101_SIG_DL_5G 13
+#define ACC101_SIG_DL_5G_LAST 15
+#define ACC101_SIG_UL_4G 16
+#define ACC101_SIG_UL_4G_LAST 19
+#define ACC101_SIG_DL_4G 27
+#define ACC101_SIG_DL_4G_LAST 31
#define ACC101_NUM_ACCS 5
#define ACC101_ACCMAP_0 0
#define ACC101_ACCMAP_1 2
@@ -132,7 +152,23 @@
#define ACC101_K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
#define ACC101_K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
+/* ACC101 Configuration */
+#define ACC101_CFG_DMA_ERROR 0x3D7
+#define ACC101_CFG_AXI_CACHE 0x11
+#define ACC101_CFG_QMGR_HI_P 0x0F0F
+#define ACC101_CFG_PCI_AXI 0xC003
+#define ACC101_CFG_PCI_BRIDGE 0x40006033
+#define ACC101_ENGINE_OFFSET 0x1000
+#define ACC101_ENGINES_MAX 9
#define ACC101_LONG_WAIT 1000
+#define ACC101_GPEX_AXIMAP_NUM 17
+#define ACC101_CLOCK_GATING_EN 0x30000
+#define ACC101_DMA_INBOUND 0x104
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC101_HARQ_DDR (512 * 1)
+#define ACC101_MS_IN_US (1000)
/* ACC101 DMA Descriptor triplet */
struct acc101_dma_triplet {
@@ -1,3 +1,10 @@
DPDK_22 {
local: *;
};
+
+EXPERIMENTAL {
+ global:
+
+ rte_acc101_configure;
+
+};