diff mbox series

[v2,4/5] baseband/acc100: start explicitly PF Monitor from PMD

Message ID 1651083423-33202-5-git-send-email-nicolas.chautru@intel.com (mailing list archive)
State Superseded, archived
Delegated to: akhil goyal
Headers
Series drivers/baseband: PMD to support ACC101 device |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Chautru, Nicolas April 27, 2022, 6:17 p.m. UTC 
  Ensure the performance monitor is restarted in case this
is reset after VF FLR.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++
 drivers/baseband/acc100/rte_acc100_pmd.h | 6 ++++++
 2 files changed, 10 insertions(+)

Comments

Tom Rix May 8, 2022, 1:44 p.m. UTC | #1 
On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> Ensure the performance monitor is restarted in case this
> is reset after VF FLR.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
>   drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++
>   drivers/baseband/acc100/rte_acc100_pmd.h | 6 ++++++
>   2 files changed, 10 insertions(+)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index b03cedc..b588f5f 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -263,6 +263,10 @@
>   					& 0xF;
>   	}
>   
> +	/* Start Pmon */
> +	acc100_reg_write(d, reg_addr->pmon_ctrl_a, 0x2);
> +	acc100_reg_write(d, reg_addr->pmon_ctrl_b, 0x2);

This looks like an acc100 bug fix, so it should be split from the acc101 
pathset.

Where this code is added is fetch_acc100_config, a function that does reads.

Though convenient, this is likely not the best place to put the writes

Tom

> +
>   	/* Read PF mode */
>   	if (d->pf_device) {
>   		reg_mode = acc100_reg_read(d, HWPfHiPfMode);
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
> index 6438031..f126cc0 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> @@ -475,6 +475,8 @@ struct acc100_registry_addr {
>   	unsigned int depth_log1_offset;
>   	unsigned int qman_group_func;
>   	unsigned int ddr_range;
> +	unsigned int pmon_ctrl_a;
> +	unsigned int pmon_ctrl_b;
>   };
>   
>   /* Structure holding registry addresses for PF */
> @@ -504,6 +506,8 @@ struct acc100_registry_addr {
>   	.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
>   	.qman_group_func = HWPfQmgrGrpFunction0,
>   	.ddr_range = HWPfDmaVfDdrBaseRw,
> +	.pmon_ctrl_a = HWPfPermonACntrlRegVf,
> +	.pmon_ctrl_b = HWPfPermonBCntrlRegVf,
>   };
>   
>   /* Structure holding registry addresses for VF */
> @@ -533,6 +537,8 @@ struct acc100_registry_addr {
>   	.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
>   	.qman_group_func = HWVfQmgrGrpFunction0Vf,
>   	.ddr_range = HWVfDmaDdrBaseRangeRoVf,
> +	.pmon_ctrl_a = HWVfPmACntrlRegVf,
> +	.pmon_ctrl_b = HWVfPmBCntrlRegVf,
>   };
>   
>   /* Structure associated with each queue. */
Chautru, Nicolas May 9, 2022, 10:07 p.m. UTC | #2 
Hi Tom, 

> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Sunday, May 8, 2022 6:45 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
> Subject: Re: [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from
> PMD
> 
> 
> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> > Ensure the performance monitor is restarted in case this is reset
> > after VF FLR.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> >   drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++
> >   drivers/baseband/acc100/rte_acc100_pmd.h | 6 ++++++
> >   2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index b03cedc..b588f5f 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -263,6 +263,10 @@
> >   					& 0xF;
> >   	}
> >
> > +	/* Start Pmon */
> > +	acc100_reg_write(d, reg_addr->pmon_ctrl_a, 0x2);
> > +	acc100_reg_write(d, reg_addr->pmon_ctrl_b, 0x2);
> 
> This looks like an acc100 bug fix, so it should be split from the acc101 pathset.
> 
> Where this code is added is fetch_acc100_config, a function that does reads.
> 
> Though convenient, this is likely not the best place to put the writes
> 

OK fair enough It could be part of setup_queues(), Thanks.  

> Tom
> 
> > +
> >   	/* Read PF mode */
> >   	if (d->pf_device) {
> >   		reg_mode = acc100_reg_read(d, HWPfHiPfMode); diff --git
> > a/drivers/baseband/acc100/rte_acc100_pmd.h
> > b/drivers/baseband/acc100/rte_acc100_pmd.h
> > index 6438031..f126cc0 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> > @@ -475,6 +475,8 @@ struct acc100_registry_addr {
> >   	unsigned int depth_log1_offset;
> >   	unsigned int qman_group_func;
> >   	unsigned int ddr_range;
> > +	unsigned int pmon_ctrl_a;
> > +	unsigned int pmon_ctrl_b;
> >   };
> >
> >   /* Structure holding registry addresses for PF */ @@ -504,6 +506,8
> > @@ struct acc100_registry_addr {
> >   	.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
> >   	.qman_group_func = HWPfQmgrGrpFunction0,
> >   	.ddr_range = HWPfDmaVfDdrBaseRw,
> > +	.pmon_ctrl_a = HWPfPermonACntrlRegVf,
> > +	.pmon_ctrl_b = HWPfPermonBCntrlRegVf,
> >   };
> >
> >   /* Structure holding registry addresses for VF */ @@ -533,6 +537,8
> > @@ struct acc100_registry_addr {
> >   	.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
> >   	.qman_group_func = HWVfQmgrGrpFunction0Vf,
> >   	.ddr_range = HWVfDmaDdrBaseRangeRoVf,
> > +	.pmon_ctrl_a = HWVfPmACntrlRegVf,
> > +	.pmon_ctrl_b = HWVfPmBCntrlRegVf,
> >   };
> >
> >   /* Structure associated with each queue. */
diff mbox series

Patch

diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index b03cedc..b588f5f 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -263,6 +263,10 @@ 
 					& 0xF;
 	}
 
+	/* Start Pmon */
+	acc100_reg_write(d, reg_addr->pmon_ctrl_a, 0x2);
+	acc100_reg_write(d, reg_addr->pmon_ctrl_b, 0x2);
+
 	/* Read PF mode */
 	if (d->pf_device) {
 		reg_mode = acc100_reg_read(d, HWPfHiPfMode);
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index 6438031..f126cc0 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -475,6 +475,8 @@  struct acc100_registry_addr {
 	unsigned int depth_log1_offset;
 	unsigned int qman_group_func;
 	unsigned int ddr_range;
+	unsigned int pmon_ctrl_a;
+	unsigned int pmon_ctrl_b;
 };
 
 /* Structure holding registry addresses for PF */
@@ -504,6 +506,8 @@  struct acc100_registry_addr {
 	.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
 	.qman_group_func = HWPfQmgrGrpFunction0,
 	.ddr_range = HWPfDmaVfDdrBaseRw,
+	.pmon_ctrl_a = HWPfPermonACntrlRegVf,
+	.pmon_ctrl_b = HWPfPermonBCntrlRegVf,
 };
 
 /* Structure holding registry addresses for VF */
@@ -533,6 +537,8 @@  struct acc100_registry_addr {
 	.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
 	.qman_group_func = HWVfQmgrGrpFunction0Vf,
 	.ddr_range = HWVfDmaDdrBaseRangeRoVf,
+	.pmon_ctrl_a = HWVfPmACntrlRegVf,
+	.pmon_ctrl_b = HWVfPmBCntrlRegVf,
 };
 
 /* Structure associated with each queue. */