From patchwork Thu Jun 23 03:11:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 113298 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 78BACA0547; Thu, 23 Jun 2022 05:03:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6DCEB4281A; Thu, 23 Jun 2022 05:03:40 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 621F5427ED; Thu, 23 Jun 2022 05:03:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655953419; x=1687489419; h=from:to:cc:subject:date:message-id; bh=eX0AX/7SXl49fM+fKA9ZM+9JPOcSSSgssl3KZEax3iY=; b=FmucDsH43VadXDa+6W/JU2AQu6ekjUeOIql48Xkffczmf9RFlaYR6lO5 54BmuD8aOKk/Y1cnynasof7KRtl7W7auFgmDPCDOkdRhTV8/ZrC/cAMG3 wMMubuEAdpsABhKx3wZEqfaTdoUKTBS7ZVLi6gliaDcnYrX8tg95z3MmO Mp1ZEFh6gaepeNPHCtry1p41VM8z25sWzV5h3rQKjDwS9oQm6qUbTkMwS mm26u8zVVtnLAkqdttwty6o+FQuljl59cA2W+zkTID3TpqoaFmom0mRQu zC9BTxa1n2+5Qph57szqpCHOO5ixlo5EBPb46CFtaosWZoPtSHCumL8R7 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="281337125" X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="281337125" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2022 20:03:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="644514092" Received: from unknown (HELO zj-fpga-amt.sh.intel.com) ([10.238.175.102]) by fmsmga008.fm.intel.com with ESMTP; 22 Jun 2022 20:03:34 -0700 From: Wei Huang To: dev@dpdk.org, thomas@monjalon.net, nipun.gupta@nxp.com, hemant.agrawal@nxp.com Cc: stable@dpdk.org, rosen.xu@intel.com, tianfei.zhang@intel.com, qi.z.zhang@intel.com, Wei Huang Subject: [PATCH] raw/ifpga: avoid potential integer overflow Date: Wed, 22 Jun 2022 23:11:40 -0400 Message-Id: <1655953900-26199-1-git-send-email-wei.huang@intel.com> X-Mailer: git-send-email 1.8.3.1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Expression "tx_chunks * ctx->dma_buf_size" in dma_fpga_to_fpga() is evaluated using 32-bit arithmetic, which would overflow potentially. Change tx_chunks to type "uint64_t" to avoid such issue. Coverity issue: 379203 Fixes: 7d63899a5c19 ("raw/ifpga: add N3000 AFU driver") Signed-off-by: Wei Huang Acked-by: Tianfei Zhang Acked-by: Rosen Xu --- drivers/raw/ifpga/afu_pmd_n3000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/raw/ifpga/afu_pmd_n3000.c b/drivers/raw/ifpga/afu_pmd_n3000.c index 8708164..5120df5 100644 --- a/drivers/raw/ifpga/afu_pmd_n3000.c +++ b/drivers/raw/ifpga/afu_pmd_n3000.c @@ -1158,7 +1158,7 @@ static int dma_fpga_to_fpga(struct dma_afu_ctx *ctx, uint64_t dst, uint64_t src, uint64_t count_left = count; uint64_t dma_chunks = 0; uint64_t offset = 0; - uint32_t tx_chunks = 0; + uint64_t tx_chunks = 0; uint64_t *tmp_buf = NULL; int ret = 0; @@ -1213,7 +1213,7 @@ static int dma_fpga_to_fpga(struct dma_afu_ctx *ctx, uint64_t dst, uint64_t src, offset = tx_chunks * ctx->dma_buf_size; count_left -= offset; IFPGA_RAWDEV_PMD_DEBUG("0x%"PRIx64" --> 0x%"PRIx64 - " (%u...0x%"PRIx64")", + " (%"PRIu64"...0x%"PRIx64")", src, dst, tx_chunks, count_left); tmp_buf = (uint64_t *)rte_malloc(NULL, ctx->dma_buf_size, DMA_ALIGN_BYTES);