From patchwork Fri Jul 8 00:01:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 113814 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B183BA0543; Fri, 8 Jul 2022 02:16:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 626E04280D; Fri, 8 Jul 2022 02:16:08 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id A284B4069D for ; Fri, 8 Jul 2022 02:16:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657239365; x=1688775365; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=dD3A5SrLeG1cPGDVTTLL3LRxNCbHvN7cXiY37+Ge8Uw=; b=oH/aEpviybbfqLBwgj2ZbsZ6Aa66iICNL/c7xUubhr4p0v8T94V4JWuK X4Crqr3xfcMd8JEGzKPDNQbSdkTXKb85t/tjms3mj4X5p08HwQOkENT5u MIlyKU9eS9ZOmvTq/phQ1fPAHXnbGaG9kHT4iyoZQMmeOpi2FHLPo6tyY myO9ETU9Gvm9XbRvXIGi8SrMKpLH6Th2oelOB4wmScEK3zcgvz4+lMTRA z6ktNkfSidaqh96EsEMv8D6xQu6o+QgRmKYDPCLBgeQexN6kNHV5G2kdQ m6WwOA4dFSaAEqRPGMfOqeUOpGCY5A6vmxZAEW6c+wfbn+gDrnGeAMPeo w==; X-IronPort-AV: E=McAfee;i="6400,9594,10401"; a="264563076" X-IronPort-AV: E=Sophos;i="5.92,253,1650956400"; d="scan'208";a="264563076" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jul 2022 17:16:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,253,1650956400"; d="scan'208";a="591387526" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga007.jf.intel.com with ESMTP; 07 Jul 2022 17:16:03 -0700 From: Nicolas Chautru To: dev@dpdk.org, thomas@monjalon.net, gakhil@marvell.com, hemant.agrawal@nxp.com, trix@redhat.com Cc: maxime.coquelin@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com, david.marchand@redhat.com, stephen@networkplumber.org, Nicolas Chautru Subject: [PATCH v1 02/10] baseband/acc200: add HW register definitions Date: Thu, 7 Jul 2022 17:01:35 -0700 Message-Id: <1657238503-143836-3-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1657238503-143836-1-git-send-email-nicolas.chautru@intel.com> References: <1657238503-143836-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add registers list and structure to access the device. Signed-off-by: Nicolas Chautru --- drivers/baseband/acc200/acc200_pf_enum.h | 468 ++++++++++++++++++++++++ drivers/baseband/acc200/acc200_pmd.h | 588 +++++++++++++++++++++++++++++++ drivers/baseband/acc200/acc200_vf_enum.h | 89 +++++ drivers/baseband/acc200/rte_acc200_pmd.c | 2 + 4 files changed, 1147 insertions(+) create mode 100644 drivers/baseband/acc200/acc200_pf_enum.h create mode 100644 drivers/baseband/acc200/acc200_vf_enum.h diff --git a/drivers/baseband/acc200/acc200_pf_enum.h b/drivers/baseband/acc200/acc200_pf_enum.h new file mode 100644 index 0000000..e8d7001 --- /dev/null +++ b/drivers/baseband/acc200/acc200_pf_enum.h @@ -0,0 +1,468 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021 Intel Corporation + */ + +#ifndef ACC200_PF_ENUM_H +#define ACC200_PF_ENUM_H + +/* + * ACC200 Register mapping on PF BAR0 + * This is automatically generated from RDL, format may change with new RDL + * Release. + * Variable names are as is + */ +enum { + HWPfQmgrEgressQueuesTemplate = 0x0007FC00, + HWPfQmgrIngressAq = 0x00080000, + HWPfQmgrArbQAvail = 0x00A00010, + HWPfQmgrArbQBlock = 0x00A00020, + HWPfQmgrAqueueDropNotifEn = 0x00A00024, + HWPfQmgrAqueueDisableNotifEn = 0x00A00028, + HWPfQmgrSoftReset = 0x00A00038, + HWPfQmgrInitStatus = 0x00A0003C, + HWPfQmgrAramWatchdogCount = 0x00A00040, + HWPfQmgrAramWatchdogCounterEn = 0x00A00044, + HWPfQmgrAxiWatchdogCount = 0x00A00048, + HWPfQmgrAxiWatchdogCounterEn = 0x00A0004C, + HWPfQmgrProcessWatchdogCount = 0x00A00060, + HWPfQmgrProcessWatchdogCounterEn = 0x00A00054, + HWPfQmgrProcessWatchdogCounter = 0x00A00060, + HWPfQmgrMsiOverflowUpperVf = 0x00A00080, + HWPfQmgrMsiOverflowLowerVf = 0x00A00084, + HWPfQmgrMsiWatchdogOverflow = 0x00A00088, + HWPfQmgrMsiOverflowEnable = 0x00A0008C, + HWPfQmgrDebugAqPointerMemGrp = 0x00A00100, + HWPfQmgrDebugOutputArbQFifoGrp = 0x00A00140, + HWPfQmgrDebugMsiFifoGrp = 0x00A00180, + HWPfQmgrDebugAxiWdTimeoutMsiFifo = 0x00A001C0, + HWPfQmgrDebugProcessWdTimeoutMsiFifo = 0x00A001C4, + HWPfQmgrDepthLog2Grp = 0x00A00200, + HWPfQmgrTholdGrp = 0x00A00300, + HWPfQmgrGrpTmplateReg0Indx = 0x00A00600, + HWPfQmgrGrpTmplateReg1Indx = 0x00A00700, + HWPfQmgrGrpTmplateReg2indx = 0x00A00800, + HWPfQmgrGrpTmplateReg3Indx = 0x00A00900, + HWPfQmgrGrpTmplateReg4Indx = 0x00A00A00, + HWPfQmgrVfBaseAddr = 0x00A01000, + HWPfQmgrUl4GWeightRrVf = 0x00A02000, + HWPfQmgrDl4GWeightRrVf = 0x00A02100, + HWPfQmgrUl5GWeightRrVf = 0x00A02200, + HWPfQmgrDl5GWeightRrVf = 0x00A02300, + HWPfQmgrMldWeightRrVf = 0x00A02400, + HWPfQmgrArbQDepthGrp = 0x00A02F00, + HWPfQmgrGrpFunction0 = 0x00A02F40, + HWPfQmgrGrpFunction1 = 0x00A02F44, + HWPfQmgrGrpPriority = 0x00A02F48, + HWPfQmgrWeightSync = 0x00A03000, + HWPfQmgrAqEnableVf = 0x00A10000, + HWPfQmgrAqResetVf = 0x00A20000, + HWPfQmgrRingSizeVf = 0x00A20004, + HWPfQmgrGrpDepthLog20Vf = 0x00A20008, + HWPfQmgrGrpDepthLog21Vf = 0x00A2000C, + HWPfQmgrGrpFunction0Vf = 0x00A20010, + HWPfQmgrGrpFunction1Vf = 0x00A20014, + HWPfFabricM2iBufferReg = 0x00B30000, + HWPfFabricI2Mcore_reg_g0 = 0x00B31000, + HWPfFabricI2Mcore_weight_g0 = 0x00B31004, + HWPfFabricI2Mbuffer_g0 = 0x00B31008, + HWPfFabricI2Mcore_reg_g1 = 0x00B31010, + HWPfFabricI2Mcore_weight_g1 = 0x00B31014, + HWPfFabricI2Mbuffer_g1 = 0x00B31018, + HWPfFabricI2Mcore_reg_g2 = 0x00B31020, + HWPfFabricI2Mcore_weight_g2 = 0x00B31024, + HWPfFabricI2Mbuffer_g2 = 0x00B31028, + HWPfFabricI2Mcore_reg_g3 = 0x00B31030, + HWPfFabricI2Mcore_weight_g3 = 0x00B31034, + HWPfFabricI2Mbuffer_g3 = 0x00B31038, + HWPfFabricI2Mdma_weight = 0x00B31044, + HWPfFecUl5gCntrlReg = 0x00B40000, + HWPfFecUl5gI2MThreshReg = 0x00B40004, + HWPfFecUl5gVersionReg = 0x00B40100, + HWPfFecUl5gFcwStatusReg = 0x00B40104, + HWPfFecUl5gWarnReg = 0x00B40108, + HwPfFecUl5gIbDebugReg = 0x00B40200, + HwPfFecUl5gObLlrDebugReg = 0x00B40204, + HwPfFecUl5gObHarqDebugReg = 0x00B40208, + HwPfFecUl5g1CntrlReg = 0x00B41000, + HwPfFecUl5g1I2MThreshReg = 0x00B41004, + HwPfFecUl5g1VersionReg = 0x00B41100, + HwPfFecUl5g1FcwStatusReg = 0x00B41104, + HwPfFecUl5g1WarnReg = 0x00B41108, + HwPfFecUl5g1IbDebugReg = 0x00B41200, + HwPfFecUl5g1ObLlrDebugReg = 0x00B41204, + HwPfFecUl5g1ObHarqDebugReg = 0x00B41208, + HwPfFecUl5g2CntrlReg = 0x00B42000, + HwPfFecUl5g2I2MThreshReg = 0x00B42004, + HwPfFecUl5g2VersionReg = 0x00B42100, + HwPfFecUl5g2FcwStatusReg = 0x00B42104, + HwPfFecUl5g2WarnReg = 0x00B42108, + HwPfFecUl5g2IbDebugReg = 0x00B42200, + HwPfFecUl5g2ObLlrDebugReg = 0x00B42204, + HwPfFecUl5g2ObHarqDebugReg = 0x00B42208, + HwPfFecUl5g3CntrlReg = 0x00B43000, + HwPfFecUl5g3I2MThreshReg = 0x00B43004, + HwPfFecUl5g3VersionReg = 0x00B43100, + HwPfFecUl5g3FcwStatusReg = 0x00B43104, + HwPfFecUl5g3WarnReg = 0x00B43108, + HwPfFecUl5g3IbDebugReg = 0x00B43200, + HwPfFecUl5g3ObLlrDebugReg = 0x00B43204, + HwPfFecUl5g3ObHarqDebugReg = 0x00B43208, + HwPfFecUl5g4CntrlReg = 0x00B44000, + HwPfFecUl5g4I2MThreshReg = 0x00B44004, + HwPfFecUl5g4VersionReg = 0x00B44100, + HwPfFecUl5g4FcwStatusReg = 0x00B44104, + HwPfFecUl5g4WarnReg = 0x00B44108, + HwPfFecUl5g4IbDebugReg = 0x00B44200, + HwPfFecUl5g4ObLlrDebugReg = 0x00B44204, + HwPfFecUl5g4ObHarqDebugReg = 0x00B44208, + HwPfFecUl5g5CntrlReg = 0x00B45000, + HwPfFecUl5g5I2MThreshReg = 0x00B45004, + HwPfFecUl5g5VersionReg = 0x00B45100, + HwPfFecUl5g5FcwStatusReg = 0x00B45104, + HwPfFecUl5g5WarnReg = 0x00B45108, + HwPfFecUl5g5IbDebugReg = 0x00B45200, + HwPfFecUl5g5ObLlrDebugReg = 0x00B45204, + HwPfFecUl5g5ObHarqDebugReg = 0x00B45208, + HwPfFecUl5g6CntrlReg = 0x00B46000, + HwPfFecUl5g6I2MThreshReg = 0x00B46004, + HwPfFecUl5g6VersionReg = 0x00B46100, + HwPfFecUl5g6FcwStatusReg = 0x00B46104, + HwPfFecUl5g6WarnReg = 0x00B46108, + HwPfFecUl5g6IbDebugReg = 0x00B46200, + HwPfFecUl5g6ObLlrDebugReg = 0x00B46204, + HwPfFecUl5g6ObHarqDebugReg = 0x00B46208, + HwPfFecUl5g7CntrlReg = 0x00B47000, + HwPfFecUl5g7I2MThreshReg = 0x00B47004, + HwPfFecUl5g7VersionReg = 0x00B47100, + HwPfFecUl5g7FcwStatusReg = 0x00B47104, + HwPfFecUl5g7WarnReg = 0x00B47108, + HwPfFecUl5g7IbDebugReg = 0x00B47200, + HwPfFecUl5g7ObLlrDebugReg = 0x00B47204, + HwPfFecUl5g7ObHarqDebugReg = 0x00B47208, + HwPfFecUl5g8CntrlReg = 0x00B48000, + HwPfFecUl5g8I2MThreshReg = 0x00B48004, + HwPfFecUl5g8VersionReg = 0x00B48100, + HwPfFecUl5g8FcwStatusReg = 0x00B48104, + HwPfFecUl5g8WarnReg = 0x00B48108, + HwPfFecUl5g8IbDebugReg = 0x00B48200, + HwPfFecUl5g8ObLlrDebugReg = 0x00B48204, + HwPfFecUl5g8ObHarqDebugReg = 0x00B48208, + HWPfFecDl5gCntrlReg = 0x00B4F000, + HWPfFecDl5gI2MThreshReg = 0x00B4F004, + HWPfFecDl5gVersionReg = 0x00B4F100, + HWPfFecDl5gFcwStatusReg = 0x00B4F104, + HWPfFecDl5gWarnReg = 0x00B4F108, + HWPfFecUlVersionReg = 0x00B50000, + HWPfFecUlControlReg = 0x00B50004, + HWPfFecUlStatusReg = 0x00B50008, + HWPfFftConfig0 = 0x00B58004, + HWPfFftConfig1 = 0x00B58008, + HWPfFftRamPageAccess = 0x00B5800C, + HWPfFftRamOff = 0x00B58800, + HWPfFecDlVersionReg = 0x00B5F000, + HWPfFecDlClusterConfigReg = 0x00B5F004, + HWPfFecDlBurstThres = 0x00B5F00C, + HWPfFecDlClusterStatusReg0 = 0x00B5F040, + HWPfFecDlClusterStatusReg1 = 0x00B5F044, + HWPfFecDlClusterStatusReg2 = 0x00B5F048, + HWPfFecDlClusterStatusReg3 = 0x00B5F04C, + HWPfFecDlClusterStatusReg4 = 0x00B5F050, + HWPfFecDlClusterStatusReg5 = 0x00B5F054, + HWPfDmaConfig0Reg = 0x00B80000, + HWPfDmaConfig1Reg = 0x00B80004, + HWPfDmaQmgrAddrReg = 0x00B80008, + HWPfDmaSoftResetReg = 0x00B8000C, + HWPfDmaAxcacheReg = 0x00B80010, + HWPfDmaVersionReg = 0x00B80014, + HWPfDmaFrameThreshold = 0x00B80018, + HWPfDmaTimestampLo = 0x00B8001C, + HWPfDmaTimestampHi = 0x00B80020, + HWPfDmaAxiStatus = 0x00B80028, + HWPfDmaAxiControl = 0x00B8002C, + HWPfDmaNoQmgr = 0x00B80030, + HWPfDmaQosScale = 0x00B80034, + HWPfDmaQmanen = 0x00B80040, + HWPfDmaFftModeThld = 0x00B80054, + HWPfDmaQmgrQosBase = 0x00B80060, + HWPfDmaFecClkGatingEnable = 0x00B80080, + HWPfDmaPmEnable = 0x00B80084, + HWPfDmaQosEnable = 0x00B80088, + HWPfDmaHarqWeightedRrFrameThreshold = 0x00B800B0, + HWPfDmaDataSmallWeightedRrFrameThresh = 0x00B800B4, + HWPfDmaDataLargeWeightedRrFrameThresh = 0x00B800B8, + HWPfDmaInboundCbMaxSize = 0x00B800BC, + HWPfDmaInboundDrainDataSize = 0x00B800C0, + HWPfDmaEngineTypeSmall = 0x00B800C4, + HWPfDma5gdlIbThld = 0x00B800C8, + HWPfDma4gdlIbThld = 0x00B800CC, + HWPfDmafftIbThld = 0x00B800D0, + HWPfDmaVfDdrBaseRw = 0x00B80400, + HWPfDmaCmplTmOutCnt = 0x00B80800, + HWPfDmaProcTmOutCnt = 0x00B80804, + HWPfDmaStatusRrespBresp = 0x00B80810, + HWPfDmaCfgRrespBresp = 0x00B80814, + HWPfDmaStatusMemParErr = 0x00B80818, + HWPfDmaCfgMemParErrEn = 0x00B8081C, + HWPfDmaStatusDmaHwErr = 0x00B80820, + HWPfDmaCfgDmaHwErrEn = 0x00B80824, + HWPfDmaStatusFecCoreErr = 0x00B80828, + HWPfDmaCfgFecCoreErrEn = 0x00B8082C, + HWPfDmaStatusFcwDescrErr = 0x00B80830, + HWPfDmaCfgFcwDescrErrEn = 0x00B80834, + HWPfDmaStatusBlockTransmit = 0x00B80838, + HWPfDmaBlockOnErrEn = 0x00B8083C, + HWPfDmaStatusFlushDma = 0x00B80840, + HWPfDmaFlushDmaOnErrEn = 0x00B80844, + HWPfDmaStatusSdoneFifoFull = 0x00B80848, + HWPfDmaStatusDescriptorErrLoVf = 0x00B8084C, + HWPfDmaStatusDescriptorErrHiVf = 0x00B80850, + HWPfDmaStatusFcwErrLoVf = 0x00B80854, + HWPfDmaStatusFcwErrHiVf = 0x00B80858, + HWPfDmaStatusDataErrLoVf = 0x00B8085C, + HWPfDmaStatusDataErrHiVf = 0x00B80860, + HWPfDmaCfgMsiEnSoftwareErr = 0x00B80864, + HWPfDmaDescriptorSignatuture = 0x00B80868, + HWPfDmaFcwSignature = 0x00B8086C, + HWPfDmaErrorDetectionEn = 0x00B80870, + HWPfDmaErrCntrlFifoDebug = 0x00B8087C, + HWPfDmaStatusToutData = 0x00B80880, + HWPfDmaStatusToutDesc = 0x00B80884, + HWPfDmaStatusToutUnexpData = 0x00B80888, + HWPfDmaStatusToutUnexpDesc = 0x00B8088C, + HWPfDmaStatusToutProcess = 0x00B80890, + HWPfDmaConfigCtoutOutDataEn = 0x00B808A0, + HWPfDmaConfigCtoutOutDescrEn = 0x00B808A4, + HWPfDmaConfigUnexpComplDataEn = 0x00B808A8, + HWPfDmaConfigUnexpComplDescrEn = 0x00B808AC, + HWPfDmaConfigPtoutOutEn = 0x00B808B0, + HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020, + HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024, + HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028, + HWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C, + HWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040, + HWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044, + HWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048, + HWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C, + HWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060, + HWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064, + HWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068, + HWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C, + HWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080, + HWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084, + HWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088, + HWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C, + HWPDmaFftDescBaseLoRegVf = 0x00B880A0, + HWPDmaFftDescBaseHiRegVf = 0x00B880A4, + HWPDmaFftRespPtrLoRegVf = 0x00B880A8, + HWPDmaFftRespPtrHiRegVf = 0x00B880AC, + HWPfQosmonACntrlReg = 0x00B90000, + HWPfQosmonAEvalOverflow0 = 0x00B90008, + HWPfQosmonAEvalOverflow1 = 0x00B9000C, + HWPfQosmonADivTerm = 0x00B90010, + HWPfQosmonATickTerm = 0x00B90014, + HWPfQosmonAEvalTerm = 0x00B90018, + HWPfQosmonAAveTerm = 0x00B9001C, + HWPfQosmonAForceEccErr = 0x00B90020, + HWPfQosmonAEccErrDetect = 0x00B90024, + HWPfQosmonAIterationConfig0Low = 0x00B90060, + HWPfQosmonAIterationConfig0High = 0x00B90064, + HWPfQosmonAIterationConfig1Low = 0x00B90068, + HWPfQosmonAIterationConfig1High = 0x00B9006C, + HWPfQosmonAIterationConfig2Low = 0x00B90070, + HWPfQosmonAIterationConfig2High = 0x00B90074, + HWPfQosmonAIterationConfig3Low = 0x00B90078, + HWPfQosmonAIterationConfig3High = 0x00B9007C, + HWPfQosmonAEvalMemAddr = 0x00B90080, + HWPfQosmonAEvalMemData = 0x00B90084, + HWPfQosmonAXaction = 0x00B900C0, + HWPfQosmonARemThres1Vf = 0x00B90400, + HWPfQosmonAThres2Vf = 0x00B90404, + HWPfQosmonAWeiFracVf = 0x00B90408, + HWPfQosmonARrWeiVf = 0x00B9040C, + HWPfPermonACntrlRegVf = 0x00B98000, + HWPfPermonACountVf = 0x00B98008, + HWPfPermonAKCntLoVf = 0x00B98010, + HWPfPermonAKCntHiVf = 0x00B98014, + HWPfPermonADeltaCntLoVf = 0x00B98020, + HWPfPermonADeltaCntHiVf = 0x00B98024, + HWPfPermonAVersionReg = 0x00B9C000, + HWPfPermonACbControlFec = 0x00B9C0F0, + HWPfPermonADltTimerLoFec = 0x00B9C0F4, + HWPfPermonADltTimerHiFec = 0x00B9C0F8, + HWPfPermonACbCountFec = 0x00B9C100, + HWPfPermonAAccExecTimerLoFec = 0x00B9C104, + HWPfPermonAAccExecTimerHiFec = 0x00B9C108, + HWPfPermonAExecTimerMinFec = 0x00B9C200, + HWPfPermonAExecTimerMaxFec = 0x00B9C204, + HWPfPermonAControlBusMon = 0x00B9C400, + HWPfPermonAConfigBusMon = 0x00B9C404, + HWPfPermonASkipCountBusMon = 0x00B9C408, + HWPfPermonAMinLatBusMon = 0x00B9C40C, + HWPfPermonAMaxLatBusMon = 0x00B9C500, + HWPfPermonATotalLatLowBusMon = 0x00B9C504, + HWPfPermonATotalLatUpperBusMon = 0x00B9C508, + HWPfPermonATotalReqCntBusMon = 0x00B9C50C, + HWPfQosmonBCntrlReg = 0x00BA0000, + HWPfQosmonBEvalOverflow0 = 0x00BA0008, + HWPfQosmonBEvalOverflow1 = 0x00BA000C, + HWPfQosmonBDivTerm = 0x00BA0010, + HWPfQosmonBTickTerm = 0x00BA0014, + HWPfQosmonBEvalTerm = 0x00BA0018, + HWPfQosmonBAveTerm = 0x00BA001C, + HWPfQosmonBForceEccErr = 0x00BA0020, + HWPfQosmonBEccErrDetect = 0x00BA0024, + HWPfQosmonBIterationConfig0Low = 0x00BA0060, + HWPfQosmonBIterationConfig0High = 0x00BA0064, + HWPfQosmonBIterationConfig1Low = 0x00BA0068, + HWPfQosmonBIterationConfig1High = 0x00BA006C, + HWPfQosmonBIterationConfig2Low = 0x00BA0070, + HWPfQosmonBIterationConfig2High = 0x00BA0074, + HWPfQosmonBIterationConfig3Low = 0x00BA0078, + HWPfQosmonBIterationConfig3High = 0x00BA007C, + HWPfQosmonBEvalMemAddr = 0x00BA0080, + HWPfQosmonBEvalMemData = 0x00BA0084, + HWPfQosmonBXaction = 0x00BA00C0, + HWPfQosmonBRemThres1Vf = 0x00BA0400, + HWPfQosmonBThres2Vf = 0x00BA0404, + HWPfQosmonBWeiFracVf = 0x00BA0408, + HWPfQosmonBRrWeiVf = 0x00BA040C, + HWPfPermonBCntrlRegVf = 0x00BA8000, + HWPfPermonBCountVf = 0x00BA8008, + HWPfPermonBKCntLoVf = 0x00BA8010, + HWPfPermonBKCntHiVf = 0x00BA8014, + HWPfPermonBDeltaCntLoVf = 0x00BA8020, + HWPfPermonBDeltaCntHiVf = 0x00BA8024, + HWPfPermonBVersionReg = 0x00BAC000, + HWPfPermonBCbControlFec = 0x00BAC0F0, + HWPfPermonBDltTimerLoFec = 0x00BAC0F4, + HWPfPermonBDltTimerHiFec = 0x00BAC0F8, + HWPfPermonBCbCountFec = 0x00BAC100, + HWPfPermonBAccExecTimerLoFec = 0x00BAC104, + HWPfPermonBAccExecTimerHiFec = 0x00BAC108, + HWPfPermonBExecTimerMinFec = 0x00BAC200, + HWPfPermonBExecTimerMaxFec = 0x00BAC204, + HWPfPermonBControlBusMon = 0x00BAC400, + HWPfPermonBConfigBusMon = 0x00BAC404, + HWPfPermonBSkipCountBusMon = 0x00BAC408, + HWPfPermonBMinLatBusMon = 0x00BAC40C, + HWPfPermonBMaxLatBusMon = 0x00BAC500, + HWPfPermonBTotalLatLowBusMon = 0x00BAC504, + HWPfPermonBTotalLatUpperBusMon = 0x00BAC508, + HWPfPermonBTotalReqCntBusMon = 0x00BAC50C, + HWPfQosmonCCntrlReg = 0x00BB0000, + HWPfQosmonCEvalOverflow0 = 0x00BB0008, + HWPfQosmonCEvalOverflow1 = 0x00BB000C, + HWPfQosmonCDivTerm = 0x00BB0010, + HWPfQosmonCTickTerm = 0x00BB0014, + HWPfQosmonCEvalTerm = 0x00BB0018, + HWPfQosmonCAveTerm = 0x00BB001C, + HWPfQosmonCForceEccErr = 0x00BB0020, + HWPfQosmonCEccErrDetect = 0x00BB0024, + HWPfQosmonCIterationConfig0Low = 0x00BB0060, + HWPfQosmonCIterationConfig0High = 0x00BB0064, + HWPfQosmonCIterationConfig1Low = 0x00BB0068, + HWPfQosmonCIterationConfig1High = 0x00BB006C, + HWPfQosmonCIterationConfig2Low = 0x00BB0070, + HWPfQosmonCIterationConfig2High = 0x00BB0074, + HWPfQosmonCIterationConfig3Low = 0x00BB0078, + HWPfQosmonCIterationConfig3High = 0x00BB007C, + HWPfQosmonCEvalMemAddr = 0x00BB0080, + HWPfQosmonCEvalMemData = 0x00BB0084, + HWPfQosmonCXaction = 0x00BB00C0, + HWPfQosmonCRemThres1Vf = 0x00BB0400, + HWPfQosmonCThres2Vf = 0x00BB0404, + HWPfQosmonCWeiFracVf = 0x00BB0408, + HWPfQosmonCRrWeiVf = 0x00BB040C, + HWPfPermonCCntrlRegVf = 0x00BB8000, + HWPfPermonCCountVf = 0x00BB8008, + HWPfPermonCKCntLoVf = 0x00BB8010, + HWPfPermonCKCntHiVf = 0x00BB8014, + HWPfPermonCDeltaCntLoVf = 0x00BB8020, + HWPfPermonCDeltaCntHiVf = 0x00BB8024, + HWPfPermonCVersionReg = 0x00BBC000, + HWPfPermonCCbControlFec = 0x00BBC0F0, + HWPfPermonCDltTimerLoFec = 0x00BBC0F4, + HWPfPermonCDltTimerHiFec = 0x00BBC0F8, + HWPfPermonCCbCountFec = 0x00BBC100, + HWPfPermonCAccExecTimerLoFec = 0x00BBC104, + HWPfPermonCAccExecTimerHiFec = 0x00BBC108, + HWPfPermonCExecTimerMinFec = 0x00BBC200, + HWPfPermonCExecTimerMaxFec = 0x00BBC204, + HWPfPermonCControlBusMon = 0x00BBC400, + HWPfPermonCConfigBusMon = 0x00BBC404, + HWPfPermonCSkipCountBusMon = 0x00BBC408, + HWPfPermonCMinLatBusMon = 0x00BBC40C, + HWPfPermonCMaxLatBusMon = 0x00BBC500, + HWPfPermonCTotalLatLowBusMon = 0x00BBC504, + HWPfPermonCTotalLatUpperBusMon = 0x00BBC508, + HWPfPermonCTotalReqCntBusMon = 0x00BBC50C, + HWPfHiVfToPfDbellVf = 0x00C80000, + HWPfHiPfToVfDbellVf = 0x00C80008, + HWPfHiInfoRingBaseLoVf = 0x00C80010, + HWPfHiInfoRingBaseHiVf = 0x00C80014, + HWPfHiInfoRingPointerVf = 0x00C80018, + HWPfHiInfoRingIntWrEnVf = 0x00C80020, + HWPfHiInfoRingPf2VfWrEnVf = 0x00C80024, + HWPfHiMsixVectorMapperVf = 0x00C80060, + HWPfHiModuleVersionReg = 0x00C84000, + HWPfHiIosf2axiErrLogReg = 0x00C84004, + HWPfHiHardResetReg = 0x00C84008, + HWPfHi5GHardResetReg = 0x00C8400C, + HWPfHiInfoRingBaseLoRegPf = 0x00C84014, + HWPfHiInfoRingBaseHiRegPf = 0x00C84018, + HWPfHiInfoRingPointerRegPf = 0x00C8401C, + HWPfHiInfoRingIntWrEnRegPf = 0x00C84020, + HWPfHiInfoRingVf2pfLoWrEnReg = 0x00C84024, + HWPfHiInfoRingVf2pfHiWrEnReg = 0x00C84028, + HWPfHiLogParityErrStatusReg = 0x00C8402C, + HWPfHiLogDataParityErrorVfStatusLo = 0x00C84030, + HWPfHiLogDataParityErrorVfStatusHi = 0x00C84034, + HWPfHiBlockTransmitOnErrorEn = 0x00C84038, + HWPfHiCfgMsiIntWrEnRegPf = 0x00C84040, + HWPfHiCfgMsiVf2pfLoWrEnReg = 0x00C84044, + HWPfHiCfgMsiVf2pfHighWrEnReg = 0x00C84048, + HWPfHiMsixVectorMapperPf = 0x00C84060, + HWPfHiApbWrWaitTime = 0x00C84100, + HWPfHiXCounterMaxValue = 0x00C84104, + HWPfHiPfMode = 0x00C84108, + HWPfHiClkGateHystReg = 0x00C8410C, + HWPfHiSnoopBitsReg = 0x00C84110, + HWPfHiMsiDropEnableReg = 0x00C84114, + HWPfHiMsiStatReg = 0x00C84120, + HWPfHiFifoOflStatReg = 0x00C84124, + HWPfHiSectionPowerGatingReq = 0x00C84128, + HWPfHiSectionPowerGatingAck = 0x00C8412C, + HWPfHiSectionPowerGatingWaitCounter = 0x00C84130, + HWPfHiHiDebugReg = 0x00C841F4, + HWPfHiDebugMemSnoopMsiFifo = 0x00C841F8, + HWPfHiDebugMemSnoopInputFifo = 0x00C841FC, + HWPfHiMsixMappingConfig = 0x00C84200, + HWPfHiJunkReg = 0x00C8FF00, + HWPfHiMSIXBaseLoRegPf = 0x00D20000, + HWPfHiMSIXBaseHiRegPf = 0x00D20004, + HWPfHiMSIXBaseDataRegPf = 0x00D20008, + HWPfHiMSIXBaseMaskRegPf = 0x00D2000c, + HWPfHiMSIXPBABaseLoRegPf = 0x00E01000, +}; + +/* TIP PF Interrupt numbers */ +enum { + ACC200_PF_INT_QMGR_AQ_OVERFLOW = 0, + ACC200_PF_INT_DOORBELL_VF_2_PF = 1, + ACC200_PF_INT_ILLEGAL_FORMAT = 2, + ACC200_PF_INT_QMGR_DISABLED_ACCESS = 3, + ACC200_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4, + ACC200_PF_INT_DMA_DL_DESC_IRQ = 5, + ACC200_PF_INT_DMA_UL_DESC_IRQ = 6, + ACC200_PF_INT_DMA_FFT_DESC_IRQ = 7, + ACC200_PF_INT_DMA_UL5G_DESC_IRQ = 8, + ACC200_PF_INT_DMA_DL5G_DESC_IRQ = 9, + ACC200_PF_INT_DMA_MLD_DESC_IRQ = 10, + ACC200_PF_INT_ARAM_ECC_1BIT_ERR = 11, + ACC200_PF_INT_PARITY_ERR = 12, + ACC200_PF_INT_QMGR_ERR = 13, + ACC200_PF_INT_INT_REQ_OVERFLOW = 14, + ACC200_PF_INT_APB_TIMEOUT = 15, +}; + +#endif /* ACC200_PF_ENUM_H */ diff --git a/drivers/baseband/acc200/acc200_pmd.h b/drivers/baseband/acc200/acc200_pmd.h index a22ca67..b420524 100644 --- a/drivers/baseband/acc200/acc200_pmd.h +++ b/drivers/baseband/acc200/acc200_pmd.h @@ -5,6 +5,9 @@ #ifndef _RTE_ACC200_PMD_H_ #define _RTE_ACC200_PMD_H_ +#include "acc200_pf_enum.h" +#include "acc200_vf_enum.h" + /* Helper macro for logging */ #define rte_bbdev_log(level, fmt, ...) \ rte_log(RTE_LOG_ ## level, acc200_logtype, fmt "\n", \ @@ -27,6 +30,591 @@ #define RTE_ACC200_PF_DEVICE_ID (0x57C0) #define RTE_ACC200_VF_DEVICE_ID (0x57C1) +/* Define as 1 to use only a single FEC engine */ +#ifndef RTE_ACC200_SINGLE_FEC +#define RTE_ACC200_SINGLE_FEC 0 +#endif + +/* Values used in filling in descriptors */ +#define ACC200_DMA_DESC_TYPE 2 +#define ACC200_DMA_CODE_BLK_MODE 0 +#define ACC200_DMA_BLKID_FCW 1 +#define ACC200_DMA_BLKID_IN 2 +#define ACC200_DMA_BLKID_OUT_ENC 1 +#define ACC200_DMA_BLKID_OUT_HARD 1 +#define ACC200_DMA_BLKID_OUT_SOFT 2 +#define ACC200_DMA_BLKID_OUT_HARQ 3 +#define ACC200_DMA_BLKID_IN_HARQ 3 + +/* Values used in filling in decode FCWs */ +#define ACC200_FCW_TD_VER 1 +#define ACC200_FCW_TD_EXT_COLD_REG_EN 1 +#define ACC200_FCW_TD_AUTOMAP 0x0f +#define ACC200_FCW_TD_RVIDX_0 2 +#define ACC200_FCW_TD_RVIDX_1 26 +#define ACC200_FCW_TD_RVIDX_2 50 +#define ACC200_FCW_TD_RVIDX_3 74 +#define ACC200_MAX_PF_MSIX (256+32) +#define ACC200_MAX_VF_MSIX (256+7) + +/* Values used in writing to the registers */ +#define ACC200_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */ + +/* ACC200 Specific Dimensioning */ +#define ACC200_SIZE_64MBYTE (64*1024*1024) +/* Number of elements in an Info Ring */ +#define ACC200_INFO_RING_NUM_ENTRIES 1024 +/* Number of elements in HARQ layout memory + * 128M x 32kB = 4GB addressable memory + */ +#define ACC200_HARQ_LAYOUT (128 * 1024 * 1024) +/* Assume offset for HARQ in memory */ +#define ACC200_HARQ_OFFSET (32 * 1024) +#define ACC200_HARQ_OFFSET_SHIFT 15 +#define ACC200_HARQ_OFFSET_MASK 0x7ffffff +/* Mask used to calculate an index in an Info Ring array (not a byte offset) */ +#define ACC200_INFO_RING_MASK (ACC200_INFO_RING_NUM_ENTRIES-1) +/* Number of Virtual Functions ACC200 supports */ +#define ACC200_NUM_VFS 16 +#define ACC200_NUM_QGRPS 16 +#define ACC200_NUM_QGRPS_PER_WORD 8 +#define ACC200_NUM_AQS 16 +#define MAX_ENQ_BATCH_SIZE 255 +/* All ACC200 Registers alignment are 32bits = 4B */ +#define ACC200_BYTES_IN_WORD 4 +#define ACC200_MAX_E_MBUF 64000 +#define ACC200_ALGO_SPA 0 +#define ACC200_ALGO_MSA 1 + +#define ACC200_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */ +#define ACC200_VF_ID_SHIFT 4 /* Queue Index Hierarchy */ +#define ACC200_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS Mon */ +#define ACC200_TMPL_PRI_0 0x03020100 +#define ACC200_TMPL_PRI_1 0x07060504 +#define ACC200_TMPL_PRI_2 0x0b0a0908 +#define ACC200_TMPL_PRI_3 0x0f0e0d0c +#define ACC200_QUEUE_ENABLE 0x80000000 /* Bit to mark Queue as Enabled */ +#define ACC200_WORDS_IN_ARAM_SIZE (256 * 1024 / 4) +#define ACC200_FDONE 0x80000000 +#define ACC200_SDONE 0x40000000 + +#define ACC200_NUM_TMPL 32 +/* Mapping of signals for the available engines */ +#define ACC200_SIG_UL_5G 0 +#define ACC200_SIG_UL_5G_LAST 4 +#define ACC200_SIG_DL_5G 10 +#define ACC200_SIG_DL_5G_LAST 11 +#define ACC200_SIG_UL_4G 12 +#define ACC200_SIG_UL_4G_LAST 16 +#define ACC200_SIG_DL_4G 21 +#define ACC200_SIG_DL_4G_LAST 23 +#define ACC200_SIG_FFT 24 +#define ACC200_SIG_FFT_LAST 24 + +#define ACC200_NUM_ACCS 5 /* FIXMEFFT */ +#define ACC200_ACCMAP_0 0 +#define ACC200_ACCMAP_1 2 +#define ACC200_ACCMAP_2 1 +#define ACC200_ACCMAP_3 3 +#define ACC200_ACCMAP_4 4 +#define ACC200_PF_VAL 2 + +/* max number of iterations to allocate memory block for all rings */ +#define ACC200_SW_RING_MEM_ALLOC_ATTEMPTS 5 +#define ACC200_MAX_QUEUE_DEPTH 1024 +#define ACC200_DMA_MAX_NUM_POINTERS 14 +#define ACC200_DMA_MAX_NUM_POINTERS_IN 7 +#define ACC200_DMA_DESC_PADDING 8 +#define ACC200_FCW_PADDING 12 +#define ACC200_DESC_FCW_OFFSET 192 +#define ACC200_DESC_SIZE 256 +#define ACC200_DESC_OFFSET (ACC200_DESC_SIZE / 64) +#define ACC200_FCW_TE_BLEN 32 +#define ACC200_FCW_TD_BLEN 24 +#define ACC200_FCW_LE_BLEN 32 +#define ACC200_FCW_LD_BLEN 36 +#define ACC200_FCW_FFT_BLEN 28 +#define ACC200_5GUL_SIZE_0 16 +#define ACC200_5GUL_SIZE_1 40 +#define ACC200_5GUL_OFFSET_0 36 +#define ACC200_COMPANION_PTRS 8 + +#define ACC200_FCW_VER 2 +#define ACC200_MUX_5GDL_DESC 6 +#define ACC200_CMP_ENC_SIZE 20 +#define ACC200_CMP_DEC_SIZE 24 +#define ACC200_ENC_OFFSET (32) +#define ACC200_DEC_OFFSET (80) +#define ACC200_HARQ_OFFSET_THRESHOLD 1024 +#define ACC200_LIMIT_DL_MUX_BITS 534 + +/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ +#define ACC200_N_ZC_1 66 /* N = 66 Zc for BG 1 */ +#define ACC200_N_ZC_2 50 /* N = 50 Zc for BG 2 */ +#define ACC200_K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */ +#define ACC200_K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */ +#define ACC200_K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */ +#define ACC200_K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */ +#define ACC200_K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */ +#define ACC200_K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */ + +/* ACC200 Configuration */ +#define ACC200_FABRIC_MODE 0x8000103 +#define ACC200_CFG_DMA_ERROR 0x3DF +#define ACC200_CFG_AXI_CACHE 0x11 +#define ACC200_CFG_QMGR_HI_P 0x0F0F +#define ACC200_ENGINE_OFFSET 0x1000 +#define ACC200_RESET_HI 0x20100 +#define ACC200_RESET_LO 0x20000 +#define ACC200_RESET_HARD 0x1FF +#define ACC200_ENGINES_MAX 9 +#define ACC200_LONG_WAIT 1000 +#define ACC200_GPEX_AXIMAP_NUM 17 +#define ACC200_CLOCK_GATING_EN 0x30000 +#define ACC200_MS_IN_US (1000) +#define ACC200_FFT_CFG_0 0x2001 +#define ACC200_FFT_RAM_EN 0x80008000 +#define ACC200_FFT_RAM_DIS 0x0 +#define ACC200_FFT_RAM_SIZE 512 +#define ACC200_CLK_EN 0x00010A01 +#define ACC200_CLK_DIS 0x01F10A01 +#define ACC200_PG_MASK_0 0x1F +#define ACC200_PG_MASK_1 0xF +#define ACC200_PG_MASK_2 0x1 +#define ACC200_PG_MASK_3 0x0 +#define ACC200_PG_MASK_FFT 1 +#define ACC200_PG_MASK_4GUL 4 +#define ACC200_PG_MASK_5GUL 8 +#define ACC200_STATUS_WAIT 10 +#define ACC200_STATUS_TO 100 + +/* ACC200 DMA Descriptor triplet */ +struct acc200_dma_triplet { + uint64_t address; + uint32_t blen:20, + res0:4, + last:1, + dma_ext:1, + res1:2, + blkid:4; +} __rte_packed; + +/* ACC200 DMA Response Descriptor */ +union acc200_dma_rsp_desc { + uint32_t val; + struct { + uint32_t crc_status:1, + synd_ok:1, + dma_err:1, + neg_stop:1, + fcw_err:1, + output_truncat:1, + input_err:1, + timestampEn:1, + iterCountFrac:8, + iter_cnt:8, + rsrvd3:6, + sdone:1, + fdone:1; + uint32_t add_info_0; + uint32_t add_info_1; + }; +}; + + +/* ACC200 Queue Manager Enqueue PCI Register */ +union acc200_enqueue_reg_fmt { + uint32_t val; + struct { + uint32_t num_elem:8, + addr_offset:3, + rsrvd:1, + req_elem_addr:20; + }; +}; + +/* FEC 4G Uplink Frame Control Word */ +struct __rte_packed acc200_fcw_td { + uint8_t fcw_ver:4, + num_maps:4; + uint8_t filler:6, + rsrvd0:1, + bypass_sb_deint:1; + uint16_t k_pos; + uint16_t k_neg; + uint8_t c_neg; + uint8_t c; + uint32_t ea; + uint32_t eb; + uint8_t cab; + uint8_t k0_start_col; + uint8_t rsrvd1; + uint8_t code_block_mode:1, + turbo_crc_type:1, + rsrvd2:3, + bypass_teq:1, + soft_output_en:1, + ext_td_cold_reg_en:1; + union { /* External Cold register */ + uint32_t ext_td_cold_reg; + struct { + uint32_t min_iter:4, + max_iter:4, + ext_scale:5, + rsrvd3:3, + early_stop_en:1, + sw_soft_out_dis:1, + sw_et_cont:1, + sw_soft_out_saturation:1, + half_iter_on:1, + raw_decoder_input_on:1, /* Unused */ + rsrvd4:10; + }; + }; +}; + +/* FEC 5GNR Uplink Frame Control Word */ +struct __rte_packed acc200_fcw_ld { + uint32_t FCWversion:4, + qm:4, + nfiller:11, + BG:1, + Zc:9, + cnu_algo:1, + synd_precoder:1, + synd_post:1; + uint32_t ncb:16, + k0:16; + uint32_t rm_e:24, + hcin_en:1, + hcout_en:1, + crc_select:1, + bypass_dec:1, + bypass_intlv:1, + so_en:1, + so_bypass_rm:1, + so_bypass_intlv:1; + uint32_t hcin_offset:16, + hcin_size0:16; + uint32_t hcin_size1:16, + hcin_decomp_mode:3, + llr_pack_mode:1, + hcout_comp_mode:3, + res2:1, + dec_convllr:4, + hcout_convllr:4; + uint32_t itmax:7, + itstop:1, + so_it:7, + res3:1, + hcout_offset:16; + uint32_t hcout_size0:16, + hcout_size1:16; + uint32_t gain_i:8, + gain_h:8, + negstop_th:16; + uint32_t negstop_it:7, + negstop_en:1, + tb_crc_select:2, + res4:2, + tb_trailer_size:20; +}; + +/* FEC 4G Downlink Frame Control Word */ +struct __rte_packed acc200_fcw_te { + uint16_t k_neg; + uint16_t k_pos; + uint8_t c_neg; + uint8_t c; + uint8_t filler; + uint8_t cab; + uint32_t ea:17, + rsrvd0:15; + uint32_t eb:17, + rsrvd1:15; + uint16_t ncb_neg; + uint16_t ncb_pos; + uint8_t rv_idx0:2, + rsrvd2:2, + rv_idx1:2, + rsrvd3:2; + uint8_t bypass_rv_idx0:1, + bypass_rv_idx1:1, + bypass_rm:1, + rsrvd4:5; + uint8_t rsrvd5:1, + rsrvd6:3, + code_block_crc:1, + rsrvd7:3; + uint8_t code_block_mode:1, + rsrvd8:7; + uint64_t rsrvd9; +}; + +/* FEC 5GNR Downlink Frame Control Word */ +struct __rte_packed acc200_fcw_le { + uint32_t FCWversion:4, + qm:4, + nfiller:11, + BG:1, + Zc:9, + res0:3; + uint32_t ncb:16, + k0:16; + uint32_t rm_e:24, + res1:2, + crc_select:1, + res2:1, + bypass_intlv:1, + res3:3; + uint32_t res4_a:12, + mcb_count:3, + res4_b:17; + uint32_t res5; + uint32_t res6; + uint32_t res7; + uint32_t res8; +}; + +/* FFT Frame Control Word */ +struct __rte_packed acc200_fcw_fft { + uint32_t in_frame_size:16, + leading_pad_size:16; + uint32_t out_frame_size:16, + leading_depad_size:16; + uint32_t cs_window_sel; + uint32_t cs_window_sel2:16, + cs_enable_bmap:16; + uint32_t num_antennas:8, + idft_size:8, + dft_size:8, + cs_offset:8; + uint32_t idft_shift:8, + dft_shift:8, + cs_multiplier:16; + uint32_t bypass:2, + res:30; +}; + +struct __rte_packed acc200_pad_ptr { + void *op_addr; + uint64_t pad1; /* pad to 64 bits */ +}; + +struct __rte_packed acc200_ptrs { + struct acc200_pad_ptr ptr[ACC200_COMPANION_PTRS]; +}; + +/* ACC200 DMA Request Descriptor */ +struct __rte_packed acc200_dma_req_desc { + union { + struct{ + uint32_t type:4, + rsrvd0:26, + sdone:1, + fdone:1; + uint32_t ib_ant_offset:16, + res2:12, + num_ant:4; + uint32_t ob_ant_offset:16, + ob_cyc_offset:12, + num_cs:4; + uint32_t pass_param:8, + sdone_enable:1, + irq_enable:1, + timeStampEn:1, + res0:5, + numCBs:4, + res1:4, + m2dlen:4, + d2mlen:4; + }; + struct{ + uint32_t word0; + uint32_t word1; + uint32_t word2; + uint32_t word3; + }; + }; + struct acc200_dma_triplet data_ptrs[ACC200_DMA_MAX_NUM_POINTERS]; + + /* Virtual addresses used to retrieve SW context info */ + union { + void *op_addr; + uint64_t pad1; /* pad to 64 bits */ + }; + /* + * Stores additional information needed for driver processing: + * - last_desc_in_batch - flag used to mark last descriptor (CB) + * in batch + * - cbs_in_tb - stores information about total number of Code Blocks + * in currently processed Transport Block + */ + union { + struct { + union { + struct acc200_fcw_ld fcw_ld; + struct acc200_fcw_td fcw_td; + struct acc200_fcw_le fcw_le; + struct acc200_fcw_te fcw_te; + struct acc200_fcw_fft fcw_fft; + uint32_t pad2[ACC200_FCW_PADDING]; + }; + uint32_t last_desc_in_batch :8, + cbs_in_tb:8, + pad4 : 16; + }; + uint64_t pad3[ACC200_DMA_DESC_PADDING]; /* pad to 64 bits */ + }; +}; + +/* ACC200 DMA Descriptor */ +union acc200_dma_desc { + struct acc200_dma_req_desc req; + union acc200_dma_rsp_desc rsp; + uint64_t atom_hdr; +}; + + +/* Union describing Info Ring entry */ +union acc200_harq_layout_data { + uint32_t val; + struct { + uint16_t offset; + uint16_t size0; + }; +} __rte_packed; + + +/* Union describing Info Ring entry */ +union acc200_info_ring_data { + uint32_t val; + struct { + union { + uint16_t detailed_info; + struct { + uint16_t aq_id: 4; + uint16_t qg_id: 4; + uint16_t vf_id: 6; + uint16_t reserved: 2; + }; + }; + uint16_t int_nb: 7; + uint16_t msi_0: 1; + uint16_t vf2pf: 6; + uint16_t loop: 1; + uint16_t valid: 1; + }; +} __rte_packed; + +struct acc200_registry_addr { + unsigned int dma_ring_dl5g_hi; + unsigned int dma_ring_dl5g_lo; + unsigned int dma_ring_ul5g_hi; + unsigned int dma_ring_ul5g_lo; + unsigned int dma_ring_dl4g_hi; + unsigned int dma_ring_dl4g_lo; + unsigned int dma_ring_ul4g_hi; + unsigned int dma_ring_ul4g_lo; + unsigned int dma_ring_fft_hi; + unsigned int dma_ring_fft_lo; + unsigned int ring_size; + unsigned int info_ring_hi; + unsigned int info_ring_lo; + unsigned int info_ring_en; + unsigned int info_ring_ptr; + unsigned int tail_ptrs_dl5g_hi; + unsigned int tail_ptrs_dl5g_lo; + unsigned int tail_ptrs_ul5g_hi; + unsigned int tail_ptrs_ul5g_lo; + unsigned int tail_ptrs_dl4g_hi; + unsigned int tail_ptrs_dl4g_lo; + unsigned int tail_ptrs_ul4g_hi; + unsigned int tail_ptrs_ul4g_lo; + unsigned int tail_ptrs_fft_hi; + unsigned int tail_ptrs_fft_lo; + unsigned int depth_log0_offset; + unsigned int depth_log1_offset; + unsigned int qman_group_func; + unsigned int hi_mode; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; + unsigned int pmon_ctrl_c; +}; + +/* Structure holding registry addresses for PF */ +static const struct acc200_registry_addr pf_reg_addr = { + .dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf, + .dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf, + .dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf, + .dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf, + .dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf, + .dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf, + .dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf, + .dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf, + .dma_ring_fft_hi = HWPDmaFftDescBaseHiRegVf, + .dma_ring_fft_lo = HWPDmaFftDescBaseLoRegVf, + .ring_size = HWPfQmgrRingSizeVf, + .info_ring_hi = HWPfHiInfoRingBaseHiRegPf, + .info_ring_lo = HWPfHiInfoRingBaseLoRegPf, + .info_ring_en = HWPfHiInfoRingIntWrEnRegPf, + .info_ring_ptr = HWPfHiInfoRingPointerRegPf, + .tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf, + .tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf, + .tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf, + .tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf, + .tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf, + .tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf, + .tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf, + .tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf, + .tail_ptrs_fft_hi = HWPDmaFftRespPtrHiRegVf, + .tail_ptrs_fft_lo = HWPDmaFftRespPtrLoRegVf, + .depth_log0_offset = HWPfQmgrGrpDepthLog20Vf, + .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, + .qman_group_func = HWPfQmgrGrpFunction0, + .hi_mode = HWPfHiMsixVectorMapperPf, + .pmon_ctrl_a = HWPfPermonACntrlRegVf, + .pmon_ctrl_b = HWPfPermonBCntrlRegVf, + .pmon_ctrl_c = HWPfPermonCCntrlRegVf, +}; + +/* Structure holding registry addresses for VF */ +static const struct acc200_registry_addr vf_reg_addr = { + .dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf, + .dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf, + .dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf, + .dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf, + .dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf, + .dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf, + .dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf, + .dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf, + .dma_ring_fft_hi = HWVfDmaFftDescBaseHiRegVf, + .dma_ring_fft_lo = HWVfDmaFftDescBaseLoRegVf, + .ring_size = HWVfQmgrRingSizeVf, + .info_ring_hi = HWVfHiInfoRingBaseHiVf, + .info_ring_lo = HWVfHiInfoRingBaseLoVf, + .info_ring_en = HWVfHiInfoRingIntWrEnVf, + .info_ring_ptr = HWVfHiInfoRingPointerVf, + .tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf, + .tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf, + .tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf, + .tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf, + .tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf, + .tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf, + .tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf, + .tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf, + .tail_ptrs_fft_hi = HWVfDmaFftRespPtrHiRegVf, + .tail_ptrs_fft_lo = HWVfDmaFftRespPtrLoRegVf, + .depth_log0_offset = HWVfQmgrGrpDepthLog20Vf, + .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf, + .qman_group_func = HWVfQmgrGrpFunction0Vf, + .hi_mode = HWVfHiMsixVectorMapperVf, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, + .pmon_ctrl_c = HWVfPmCCntrlRegVf, +}; + + /* Private data structure for each ACC200 device */ struct acc200_device { void *mmio_base; /**< Base address of MMIO registers (BAR0) */ diff --git a/drivers/baseband/acc200/acc200_vf_enum.h b/drivers/baseband/acc200/acc200_vf_enum.h new file mode 100644 index 0000000..616edb6 --- /dev/null +++ b/drivers/baseband/acc200/acc200_vf_enum.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2021 Intel Corporation + */ + +#ifndef ACC200_VF_ENUM_H +#define ACC200_VF_ENUM_H + +/* + * ACC200 Register mapping on VF BAR0 + * This is automatically generated from RDL, format may change with new RDL + */ +enum { + HWVfQmgrIngressAq = 0x00000000, + HWVfHiVfToPfDbellVf = 0x00000800, + HWVfHiPfToVfDbellVf = 0x00000808, + HWVfHiInfoRingBaseLoVf = 0x00000810, + HWVfHiInfoRingBaseHiVf = 0x00000814, + HWVfHiInfoRingPointerVf = 0x00000818, + HWVfHiInfoRingIntWrEnVf = 0x00000820, + HWVfHiInfoRingPf2VfWrEnVf = 0x00000824, + HWVfHiMsixVectorMapperVf = 0x00000860, + HWVfDmaFec5GulDescBaseLoRegVf = 0x00000920, + HWVfDmaFec5GulDescBaseHiRegVf = 0x00000924, + HWVfDmaFec5GulRespPtrLoRegVf = 0x00000928, + HWVfDmaFec5GulRespPtrHiRegVf = 0x0000092C, + HWVfDmaFec5GdlDescBaseLoRegVf = 0x00000940, + HWVfDmaFec5GdlDescBaseHiRegVf = 0x00000944, + HWVfDmaFec5GdlRespPtrLoRegVf = 0x00000948, + HWVfDmaFec5GdlRespPtrHiRegVf = 0x0000094C, + HWVfDmaFec4GulDescBaseLoRegVf = 0x00000960, + HWVfDmaFec4GulDescBaseHiRegVf = 0x00000964, + HWVfDmaFec4GulRespPtrLoRegVf = 0x00000968, + HWVfDmaFec4GulRespPtrHiRegVf = 0x0000096C, + HWVfDmaFec4GdlDescBaseLoRegVf = 0x00000980, + HWVfDmaFec4GdlDescBaseHiRegVf = 0x00000984, + HWVfDmaFec4GdlRespPtrLoRegVf = 0x00000988, + HWVfDmaFec4GdlRespPtrHiRegVf = 0x0000098C, + HWVfDmaFftDescBaseLoRegVf = 0x000009A0, + HWVfDmaFftDescBaseHiRegVf = 0x000009A4, + HWVfDmaFftRespPtrLoRegVf = 0x000009A8, + HWVfDmaFftRespPtrHiRegVf = 0x000009AC, + HWVfQmgrAqResetVf = 0x00000E00, + HWVfQmgrRingSizeVf = 0x00000E04, + HWVfQmgrGrpDepthLog20Vf = 0x00000E08, + HWVfQmgrGrpDepthLog21Vf = 0x00000E0C, + HWVfQmgrGrpFunction0Vf = 0x00000E10, + HWVfQmgrGrpFunction1Vf = 0x00000E14, + HWVfPmACntrlRegVf = 0x00000F40, + HWVfPmACountVf = 0x00000F48, + HWVfPmAKCntLoVf = 0x00000F50, + HWVfPmAKCntHiVf = 0x00000F54, + HWVfPmADeltaCntLoVf = 0x00000F60, + HWVfPmADeltaCntHiVf = 0x00000F64, + HWVfPmBCntrlRegVf = 0x00000F80, + HWVfPmBCountVf = 0x00000F88, + HWVfPmBKCntLoVf = 0x00000F90, + HWVfPmBKCntHiVf = 0x00000F94, + HWVfPmBDeltaCntLoVf = 0x00000FA0, + HWVfPmBDeltaCntHiVf = 0x00000FA4, + HWVfPmCCntrlRegVf = 0x00000FC0, + HWVfPmCCountVf = 0x00000FC8, + HWVfPmCKCntLoVf = 0x00000FD0, + HWVfPmCKCntHiVf = 0x00000FD4, + HWVfPmCDeltaCntLoVf = 0x00000FE0, + HWVfPmCDeltaCntHiVf = 0x00000FE4 +}; + +/* TIP VF Interrupt numbers */ +enum { + ACC200_VF_INT_QMGR_AQ_OVERFLOW = 0, + ACC200_VF_INT_DOORBELL_PF_2_VF = 1, + ACC200_VF_INT_ILLEGAL_FORMAT = 2, + ACC200_VF_INT_QMGR_DISABLED_ACCESS = 3, + ACC200_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4, + ACC200_VF_INT_DMA_DL_DESC_IRQ = 5, + ACC200_VF_INT_DMA_UL_DESC_IRQ = 6, + ACC200_VF_INT_DMA_FFT_DESC_IRQ = 7, + ACC200_VF_INT_DMA_UL5G_DESC_IRQ = 8, + ACC200_VF_INT_DMA_DL5G_DESC_IRQ = 9, + ACC200_VF_INT_DMA_MLD_DESC_IRQ = 10, +}; + +/* TIP VF2PF Comms */ +enum { + ACC200_VF2PF_STATUS_REQUEST = 0, + ACC200_VF2PF_USING_VF = 1, +}; + +#endif /* ACC200_VF_ENUM_H */ diff --git a/drivers/baseband/acc200/rte_acc200_pmd.c b/drivers/baseband/acc200/rte_acc200_pmd.c index 4103e48..70b6cc5 100644 --- a/drivers/baseband/acc200/rte_acc200_pmd.c +++ b/drivers/baseband/acc200/rte_acc200_pmd.c @@ -34,6 +34,8 @@ acc200_dev_close(struct rte_bbdev *dev) { RTE_SET_USED(dev); + /* Ensure all in flight HW transactions are completed */ + usleep(ACC200_LONG_WAIT); return 0; }