From patchwork Fri Feb 23 19:03:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tyler Retzlaff X-Patchwork-Id: 137123 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 698B043BA4; Fri, 23 Feb 2024 20:06:05 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BD54342DB6; Fri, 23 Feb 2024 20:04:38 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id D2B744029A for ; Fri, 23 Feb 2024 20:04:18 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1086) id 4A91420B74D5; Fri, 23 Feb 2024 11:04:16 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4A91420B74D5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1708715057; bh=bQFHXqeoycDtocIPhUh5S8gHrS91WUGnxJOVh9jMKro=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n5QvQCBeFRUUYBL4czsYlPsDnofKCy0MaTACirpjYzkGGnDoI2E1xQMv8QdCFlkAI tv68smoqpAS5/qdyO6/7aOwMPDPnMEjC2aef6I0awAionHO2TsNf5txXXi0H6+AwEb aTv1phzPrOwlqohW7vPo47i4Zg/q9DTz+woydqr0= From: Tyler Retzlaff To: dev@dpdk.org Cc: Andrew Rybchenko , Bruce Richardson , Chengwen Feng , Cristian Dumitrescu , David Christensen , David Hunt , Ferruh Yigit , Honnappa Nagarahalli , Jasvinder Singh , Jerin Jacob , Kevin Laatz , Konstantin Ananyev , Min Zhou , Ruifeng Wang , Sameh Gobriel , Stanislaw Kardach , Thomas Monjalon , Vladimir Medvedkin , Yipeng Wang , Tyler Retzlaff Subject: [PATCH v5 21/39] power: use C11 alignas Date: Fri, 23 Feb 2024 11:03:56 -0800 Message-Id: <1708715054-22386-22-git-send-email-roretzla@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1708715054-22386-1-git-send-email-roretzla@linux.microsoft.com> References: <1707873986-29352-1-git-send-email-roretzla@linux.microsoft.com> <1708715054-22386-1-git-send-email-roretzla@linux.microsoft.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The current location used for __rte_aligned(a) for alignment of types and variables is not compatible with MSVC. There is only a single location accepted by both toolchains. For variables standard C11 offers alignas(a) supported by conformant compilers i.e. both MSVC and GCC. For types the standard offers no alignment facility that compatibly interoperates with C and C++ but may be achieved by relocating the placement of __rte_aligned(a) to the aforementioned location accepted by all currently supported toolchains. To allow alignment for both compilers do the following: * Move __rte_aligned from the end of {struct,union} definitions to be between {struct,union} and tag. The placement between {struct,union} and the tag allows the desired alignment to be imparted on the type regardless of the toolchain being used for all of GCC, LLVM, MSVC compilers building both C and C++. * Replace use of __rte_aligned(a) on variables/fields with alignas(a). Signed-off-by: Tyler Retzlaff Acked-by: Morten Brørup --- lib/power/power_acpi_cpufreq.c | 4 ++-- lib/power/power_amd_pstate_cpufreq.c | 4 ++-- lib/power/power_cppc_cpufreq.c | 4 ++-- lib/power/power_intel_uncore.c | 4 ++-- lib/power/power_pstate_cpufreq.c | 4 ++-- lib/power/rte_power_pmd_mgmt.c | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/lib/power/power_acpi_cpufreq.c b/lib/power/power_acpi_cpufreq.c index f8d978d..81996e1 100644 --- a/lib/power/power_acpi_cpufreq.c +++ b/lib/power/power_acpi_cpufreq.c @@ -41,7 +41,7 @@ enum power_state { /** * Power info per lcore. */ -struct acpi_power_info { +struct __rte_cache_aligned acpi_power_info { unsigned int lcore_id; /**< Logical core id */ uint32_t freqs[RTE_MAX_LCORE_FREQS]; /**< Frequency array */ uint32_t nb_freqs; /**< number of available freqs */ @@ -51,7 +51,7 @@ struct acpi_power_info { RTE_ATOMIC(uint32_t) state; /**< Power in use state */ uint16_t turbo_available; /**< Turbo Boost available */ uint16_t turbo_enable; /**< Turbo Boost enable/disable */ -} __rte_cache_aligned; +}; static struct acpi_power_info lcore_power_info[RTE_MAX_LCORE]; diff --git a/lib/power/power_amd_pstate_cpufreq.c b/lib/power/power_amd_pstate_cpufreq.c index 028f844..090a0d9 100644 --- a/lib/power/power_amd_pstate_cpufreq.c +++ b/lib/power/power_amd_pstate_cpufreq.c @@ -45,7 +45,7 @@ enum power_state { /** * Power info per lcore. */ -struct amd_pstate_power_info { +struct __rte_cache_aligned amd_pstate_power_info { uint32_t lcore_id; /**< Logical core id */ RTE_ATOMIC(uint32_t) state; /**< Power in use state */ FILE *f; /**< FD of scaling_setspeed */ @@ -58,7 +58,7 @@ struct amd_pstate_power_info { uint16_t turbo_enable; /**< Turbo Boost enable/disable */ uint32_t nb_freqs; /**< number of available freqs */ uint32_t freqs[RTE_MAX_LCORE_FREQS]; /**< Frequency array */ -} __rte_cache_aligned; +}; static struct amd_pstate_power_info lcore_power_info[RTE_MAX_LCORE]; diff --git a/lib/power/power_cppc_cpufreq.c b/lib/power/power_cppc_cpufreq.c index 3ddf39b..32aaacb 100644 --- a/lib/power/power_cppc_cpufreq.c +++ b/lib/power/power_cppc_cpufreq.c @@ -49,7 +49,7 @@ enum power_state { /** * Power info per lcore. */ -struct cppc_power_info { +struct __rte_cache_aligned cppc_power_info { unsigned int lcore_id; /**< Logical core id */ RTE_ATOMIC(uint32_t) state; /**< Power in use state */ FILE *f; /**< FD of scaling_setspeed */ @@ -61,7 +61,7 @@ struct cppc_power_info { uint16_t turbo_enable; /**< Turbo Boost enable/disable */ uint32_t nb_freqs; /**< number of available freqs */ uint32_t freqs[RTE_MAX_LCORE_FREQS]; /**< Frequency array */ -} __rte_cache_aligned; +}; static struct cppc_power_info lcore_power_info[RTE_MAX_LCORE]; diff --git a/lib/power/power_intel_uncore.c b/lib/power/power_intel_uncore.c index 3ce8fcc..9c152e4 100644 --- a/lib/power/power_intel_uncore.c +++ b/lib/power/power_intel_uncore.c @@ -29,7 +29,7 @@ "/sys/devices/system/cpu/intel_uncore_frequency/package_%02u_die_%02u/initial_min_freq_khz" -struct uncore_power_info { +struct __rte_cache_aligned uncore_power_info { unsigned int die; /* Core die id */ unsigned int pkg; /* Package id */ uint32_t freqs[MAX_UNCORE_FREQS]; /* Frequency array */ @@ -41,7 +41,7 @@ struct uncore_power_info { uint32_t org_max_freq; /* Original max freq of uncore */ uint32_t init_max_freq; /* System max uncore freq */ uint32_t init_min_freq; /* System min uncore freq */ -} __rte_cache_aligned; +}; static struct uncore_power_info uncore_info[RTE_MAX_NUMA_NODES][MAX_NUMA_DIE]; diff --git a/lib/power/power_pstate_cpufreq.c b/lib/power/power_pstate_cpufreq.c index 73138dc..2343121 100644 --- a/lib/power/power_pstate_cpufreq.c +++ b/lib/power/power_pstate_cpufreq.c @@ -49,7 +49,7 @@ enum power_state { POWER_UNKNOWN }; -struct pstate_power_info { +struct __rte_cache_aligned pstate_power_info { unsigned int lcore_id; /**< Logical core id */ uint32_t freqs[RTE_MAX_LCORE_FREQS]; /**< Frequency array */ uint32_t nb_freqs; /**< number of available freqs */ @@ -64,7 +64,7 @@ struct pstate_power_info { uint16_t turbo_available; /**< Turbo Boost available */ uint16_t turbo_enable; /**< Turbo Boost enable/disable */ uint16_t priority_core; /**< High Performance core */ -} __rte_cache_aligned; +}; static struct pstate_power_info lcore_power_info[RTE_MAX_LCORE]; diff --git a/lib/power/rte_power_pmd_mgmt.c b/lib/power/rte_power_pmd_mgmt.c index 591fc69..b1c18a5 100644 --- a/lib/power/rte_power_pmd_mgmt.c +++ b/lib/power/rte_power_pmd_mgmt.c @@ -55,7 +55,7 @@ struct queue_list_entry { const struct rte_eth_rxtx_callback *cb; }; -struct pmd_core_cfg { +struct __rte_cache_aligned pmd_core_cfg { TAILQ_HEAD(queue_list_head, queue_list_entry) head; /**< List of queues associated with this lcore */ size_t n_queues; @@ -68,7 +68,7 @@ struct pmd_core_cfg { /**< Number of queues ready to enter power optimized state */ uint64_t sleep_target; /**< Prevent a queue from triggering sleep multiple times */ -} __rte_cache_aligned; +}; static struct pmd_core_cfg lcore_cfgs[RTE_MAX_LCORE]; static inline bool