Move location of __rte_aligned(a) to new conventional location. The new
placement between {struct,union} and the tag allows the desired
alignment to be imparted on the type regardless of the toolchain being
used for both C and C++. Additionally, it avoids confusion by Doxygen
when generating documentation.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
---
drivers/event/cnxk/cn10k_eventdev.h | 8 ++++----
drivers/event/cnxk/cnxk_eventdev.h | 24 ++++++++++++------------
drivers/event/cnxk/cnxk_tim_evdev.h | 4 ++--
drivers/event/cnxk/cnxk_tim_worker.c | 2 +-
4 files changed, 19 insertions(+), 19 deletions(-)
@@ -8,7 +8,7 @@
#define CN10K_SSO_DEFAULT_STASH_OFFSET -1
#define CN10K_SSO_DEFAULT_STASH_LENGTH 2
-struct cn10k_sso_hws {
+struct __rte_cache_aligned cn10k_sso_hws {
uint64_t base;
uint32_t gw_wdata;
void *lookup_mem;
@@ -19,15 +19,15 @@ struct cn10k_sso_hws {
struct cnxk_timesync_info **tstamp;
uint64_t meta_aura;
/* Add Work Fastpath data */
- int64_t *fc_mem __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) int64_t *fc_mem;
int64_t *fc_cache_space;
uintptr_t aw_lmt;
uintptr_t grp_base;
int32_t xaq_lmt;
/* Tx Fastpath data */
- uintptr_t lmt_base __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uintptr_t lmt_base;
uint64_t lso_tun_fmt;
uint8_t tx_adptr_data[];
-} __rte_cache_aligned;
+};
#endif /* __CN10K_EVENTDEV_H__ */
@@ -80,7 +80,7 @@ struct cnxk_sso_stash {
uint16_t stash_length;
};
-struct cnxk_sso_evdev {
+struct __rte_cache_aligned cnxk_sso_evdev {
struct roc_sso sso;
uint8_t max_event_queues;
uint8_t max_event_ports;
@@ -124,10 +124,10 @@ struct cnxk_sso_evdev {
uint32_t gw_mode;
uint16_t stash_cnt;
struct cnxk_sso_stash *stash_parse_data;
-} __rte_cache_aligned;
+};
/* Event port a.k.a GWS */
-struct cn9k_sso_hws {
+struct __rte_cache_aligned cn9k_sso_hws {
uint64_t base;
uint64_t gw_wdata;
void *lookup_mem;
@@ -136,15 +136,15 @@ struct cn9k_sso_hws {
/* PTP timestamp */
struct cnxk_timesync_info **tstamp;
/* Add Work Fastpath data */
- uint64_t xaq_lmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t xaq_lmt;
uint64_t *fc_mem;
uintptr_t grp_base;
/* Tx Fastpath data */
- uint64_t lso_tun_fmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t lso_tun_fmt;
uint8_t tx_adptr_data[];
-} __rte_cache_aligned;
+};
-struct cn9k_sso_hws_dual {
+struct __rte_cache_aligned cn9k_sso_hws_dual {
uint64_t base[2]; /* Ping and Pong */
uint64_t gw_wdata;
void *lookup_mem;
@@ -154,18 +154,18 @@ struct cn9k_sso_hws_dual {
/* PTP timestamp */
struct cnxk_timesync_info **tstamp;
/* Add Work Fastpath data */
- uint64_t xaq_lmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t xaq_lmt;
uint64_t *fc_mem;
uintptr_t grp_base;
/* Tx Fastpath data */
- uint64_t lso_tun_fmt __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) uint64_t lso_tun_fmt;
uint8_t tx_adptr_data[];
-} __rte_cache_aligned;
+};
-struct cnxk_sso_hws_cookie {
+struct __rte_cache_aligned cnxk_sso_hws_cookie {
const struct rte_eventdev *event_dev;
bool configured;
-} __rte_cache_aligned;
+};
static inline int
parse_kvargs_flag(const char *key, const char *value, void *opaque)
@@ -123,7 +123,7 @@ struct cnxk_tim_bkt {
uint64_t pad;
};
-struct cnxk_tim_ring {
+struct __rte_cache_aligned cnxk_tim_ring {
uint16_t nb_chunk_slots;
uint32_t nb_bkts;
uintptr_t tbase;
@@ -149,7 +149,7 @@ struct cnxk_tim_ring {
uint64_t nb_chunks;
uint64_t chunk_sz;
enum roc_tim_clk_src clk_src;
-} __rte_cache_aligned;
+};
struct cnxk_tim_ent {
uint64_t w0;
@@ -92,7 +92,7 @@
const uint64_t timeout_tick,
const uint16_t nb_timers, const uint8_t flags)
{
- struct cnxk_tim_ent entry[CNXK_TIM_MAX_BURST] __rte_cache_aligned;
+ alignas(RTE_CACHE_LINE_SIZE) struct cnxk_tim_ent entry[CNXK_TIM_MAX_BURST];
struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
uint16_t set_timers = 0;
uint16_t arr_idx = 0;