[dpdk-dev,3/3] pmd i40e: Enable Transmit Segmentation Offload for TCP traffic
Commit Message
From: Miroslaw Walukiewicz <miroslaw.walukiewicz@intel.com>
The patch enables the TSO HW feature for i40e PMD driver.
The feature is reported by rte_dev_info_get() if enabled.
Signed-off-by: Mirek Walukiewicz <miroslaw.walukiewicz@intel.com>
---
lib/librte_pmd_i40e/i40e_ethdev.c | 1 +
lib/librte_pmd_i40e/i40e_rxtx.c | 56 ++++++++++++++++++++++++++++++++++---
2 files changed, 53 insertions(+), 4 deletions(-)
@@ -1399,6 +1399,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
DEV_TX_OFFLOAD_IPV4_CKSUM |
DEV_TX_OFFLOAD_UDP_CKSUM |
DEV_TX_OFFLOAD_TCP_CKSUM |
+ DEV_TX_OFFLOAD_TCP_TSO |
DEV_TX_OFFLOAD_SCTP_CKSUM;
dev_info->default_rxconf = (struct rte_eth_rxconf) {
@@ -50,6 +50,8 @@
#include <rte_tcp.h>
#include <rte_sctp.h>
#include <rte_udp.h>
+#include <rte_ip.h>
+#include <rte_tcp_off.h>
#include "i40e_logs.h"
#include "i40e/i40e_prototype.h"
@@ -440,6 +442,11 @@ i40e_txd_enable_checksum(uint32_t ol_flags,
*td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
}
+ if (ol_flags & PKT_TX_TCP_TSO) {
+ *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
+ /* td offset will be set next */
+ return;
+ }
/* Enable L4 checksum offloads */
switch (ol_flags & PKT_TX_L4_MASK) {
case PKT_TX_TCP_CKSUM:
@@ -1073,12 +1080,46 @@ i40e_calc_context_desc(uint64_t flags)
#ifdef RTE_LIBRTE_IEEE1588
mask |= PKT_TX_IEEE1588_TMST;
#endif
+ /* need for context descriptor when TSO enabled */
+ mask |= PKT_TX_TCP_TSO;
if (flags & mask)
return 1;
return 0;
}
+/* set i40e TSO context descriptor */
+static inline uint64_t
+i40e_set_tso_ctx(struct rte_mbuf *mbuf, uint8_t l2_len, uint8_t l3_len, uint32_t *td_offset)
+{
+ uint64_t ctx_desc;
+ struct ipv4_hdr *ip;
+ struct tcp_hdr *th;
+ uint32_t tcp_hlen;
+ uint32_t hdrlen;
+ uint32_t paylen;
+
+ /* set mss */
+ ip = (struct ipv4_hdr *) (rte_pktmbuf_mtod(mbuf, unsigned char *) + l2_len);
+ ip->hdr_checksum = 0;
+ ip->total_length = 0;
+ th = (struct tcp_hdr *)((caddr_t)ip + l3_len);
+ th->cksum = rte_in_pseudo(ip->src_addr, ip->dst_addr, I40E_HTONS(IPPROTO_TCP));
+ tcp_hlen = (th->data_off >> 4) << 2;
+ *td_offset |= (tcp_hlen >> 2) <<
+ I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
+ hdrlen = l2_len + l3_len + tcp_hlen;
+ paylen = mbuf->pkt_len - hdrlen;
+
+ ctx_desc = ((uint64_t)mbuf->tso_segsz <<
+ I40E_TXD_CTX_QW1_MSS_SHIFT) |
+ ((uint64_t)paylen << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
+ ((uint64_t)I40E_TX_CTX_DESC_TSO <<
+ I40E_TXD_CTX_QW1_CMD_SHIFT);
+
+ return ctx_desc;
+}
+
uint16_t
i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
{
@@ -1192,12 +1233,19 @@ i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
rte_pktmbuf_free_seg(txe->mbuf);
txe->mbuf = NULL;
}
+ /* TSO enabled means no timestamp */
+ if (ol_flags & PKT_TX_TCP_TSO) {
+ cd_type_cmd_tso_mss |=
+ i40e_set_tso_ctx(tx_pkt, l2_len, l3_len, &td_offset);
+ }
+ else {
#ifdef RTE_LIBRTE_IEEE1588
- if (ol_flags & PKT_TX_IEEE1588_TMST)
- cd_type_cmd_tso_mss |=
- ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
- I40E_TXD_CTX_QW1_CMD_SHIFT);
+ if (ol_flags & PKT_TX_IEEE1588_TMST)
+ cd_type_cmd_tso_mss |=
+ ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
+ I40E_TXD_CTX_QW1_CMD_SHIFT);
#endif
+ }
ctx_txd->tunneling_params =
rte_cpu_to_le_32(cd_tunneling_params);
ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);