From patchwork Fri Mar 3 03:17:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 21169 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 8A588F971; Fri, 3 Mar 2017 03:27:30 +0100 (CET) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id C4581591E for ; Fri, 3 Mar 2017 03:26:52 +0100 (CET) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP; 02 Mar 2017 18:26:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,234,1484035200"; d="scan'208";a="71069281" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.239.129.167]) by orsmga005.jf.intel.com with ESMTP; 02 Mar 2017 18:26:51 -0800 From: Qi Zhang To: jing.d.chen@intel.com Cc: helin.zhang@intel.com, dev@dpdk.org, Qi Zhang Date: Thu, 2 Mar 2017 22:17:24 -0500 Message-Id: <20170303031727.461-15-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170303031727.461-1-qi.z.zhang@intel.com> References: <20170303031727.461-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 14/17] net/fm10k/base: add macro for geneve tunnel offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" add necessary macro to support geneve tunnel offload. Signed-off-by: Qi Zhang --- drivers/net/fm10k/base/fm10k_type.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h index d43e40c..931633d 100644 --- a/drivers/net/fm10k/base/fm10k_type.h +++ b/drivers/net/fm10k/base/fm10k_type.h @@ -194,6 +194,7 @@ struct fm10k_hw; #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000 #define FM10K_TUNNEL_CFG 0x0040 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16 +#define FM10K_TUNNEL_CFG_GENEVE 0x0041 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050) #define FM10K_SWPRI_MAX 16 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)