From patchwork Wed Mar 8 06:18:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 21578 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id BAE2FAB08; Wed, 8 Mar 2017 06:28:50 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id C9826108A for ; Wed, 8 Mar 2017 06:28:19 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Mar 2017 21:28:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,262,1486454400"; d="scan'208"; a="1139354544" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.239.129.167]) by fmsmga002.fm.intel.com with ESMTP; 07 Mar 2017 21:28:18 -0800 From: Qi Zhang To: jing.d.chen@intel.com Cc: helin.zhang@intel.com, dev@dpdk.org, Qi Zhang Date: Wed, 8 Mar 2017 01:18:51 -0500 Message-Id: <20170308061906.950-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170308061906.950-1-qi.z.zhang@intel.com> References: <20170303031727.461-1-qi.z.zhang@intel.com> <20170308061906.950-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 03/18] net/fm10k/base: expose macros needed by DPDK X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add back macros that DPDK required and remove the redundant ones in fm10k_osdep.h. Signed-off-by: Qi Zhang --- drivers/net/fm10k/base/fm10k_osdep.h | 17 ------------ drivers/net/fm10k/base/fm10k_type.h | 50 ++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 17 deletions(-) diff --git a/drivers/net/fm10k/base/fm10k_osdep.h b/drivers/net/fm10k/base/fm10k_osdep.h index f07b678..199ebd8 100644 --- a/drivers/net/fm10k/base/fm10k_osdep.h +++ b/drivers/net/fm10k/base/fm10k_osdep.h @@ -163,23 +163,6 @@ typedef int bool; #define FM10K_RXD_PKTTYPE_MASK 0x03F0 #define FM10K_RXD_PKTTYPE_SHIFT 4 -enum fm10k_rdesc_pkt_type { - /* L3 type */ - FM10K_PKTTYPE_OTHER = 0x00, - FM10K_PKTTYPE_IPV4 = 0x01, - FM10K_PKTTYPE_IPV4_EX = 0x02, - FM10K_PKTTYPE_IPV6 = 0x03, - FM10K_PKTTYPE_IPV6_EX = 0x04, - - /* L4 type */ - FM10K_PKTTYPE_TCP = 0x08, - FM10K_PKTTYPE_UDP = 0x10, - FM10K_PKTTYPE_GRE = 0x18, - FM10K_PKTTYPE_VXLAN = 0x20, - FM10K_PKTTYPE_NVGRE = 0x28, - FM10K_PKTTYPE_GENEVE = 0x30 -}; - #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */ #define FM10K_RXD_STATUS_HBO 0x0400 /* header buffer overrun */ diff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h index fe3e498..8ddfd49 100644 --- a/drivers/net/fm10k/base/fm10k_type.h +++ b/drivers/net/fm10k/base/fm10k_type.h @@ -40,6 +40,9 @@ struct fm10k_hw; #include "fm10k_osdep.h" #include "fm10k_mbx.h" +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_INTEL_VENDOR_ID 0x8086 +#endif #define FM10K_DEV_ID_PF 0x15A4 #define FM10K_DEV_ID_VF 0x15A5 #ifdef BOULDER_RAPIDS_HW @@ -125,11 +128,19 @@ struct fm10k_hw; /* Interrupt control registers */ #define FM10K_EICR 0x0006 +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_EICR_PCA_FAULT 0x00000001 +#define FM10K_EICR_THI_FAULT 0x00000004 +#define FM10K_EICR_FUM_FAULT 0x00000020 +#endif #define FM10K_EICR_FAULT_MASK 0x0000003F #define FM10K_EICR_MAILBOX 0x00000040 #define FM10K_EICR_SWITCHREADY 0x00000080 #define FM10K_EICR_SWITCHNOTREADY 0x00000100 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200 +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_EICR_SRAMERROR 0x00000400 +#endif #define FM10K_EICR_VFLR 0x00000800 #define FM10K_EICR_MAXHOLDTIME 0x00001000 #define FM10K_EIMR 0x0007 @@ -211,6 +222,9 @@ struct fm10k_hw; #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100 +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_DMA_CTRL_MINMSS_SHIFT 9 +#endif #define FM10K_DMA_CTRL_MINMSS_64 0x00008000 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000 @@ -283,6 +297,9 @@ struct fm10k_hw; #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008) +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_RXINT_TIMER_SHIFT 8 +#endif #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009) #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */ #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000 @@ -336,6 +353,9 @@ struct fm10k_hw; #define FM10K_TXQCTL_VID_MASK 0x0FFF0000 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008) +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_TXINT_TIMER_SHIFT 8 +#endif /* Tx Statistics */ #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009) @@ -374,6 +394,9 @@ struct fm10k_hw; /* Switch manager interrupt registers */ #define FM10K_IP 0x13000 #define FM10K_IP_NOTINRESET 0x00000100 +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_SRAM_IP 0x13003 +#endif /* VLAN registers */ #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000) @@ -815,6 +838,30 @@ enum fm10k_rdesc_rss_type { /* Reserved 0x9 - 0xF */ }; +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_RXD_PKTTYPE_MASK 0x03F0 +#endif +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_RXD_PKTTYPE_SHIFT 4 +#endif +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +enum fm10k_rdesc_pkt_type { + /* L3 type */ + FM10K_PKTTYPE_OTHER = 0x00, + FM10K_PKTTYPE_IPV4 = 0x01, + FM10K_PKTTYPE_IPV4_EX = 0x02, + FM10K_PKTTYPE_IPV6 = 0x03, + FM10K_PKTTYPE_IPV6_EX = 0x04, + + /* L4 type */ + FM10K_PKTTYPE_TCP = 0x08, + FM10K_PKTTYPE_UDP = 0x10, + FM10K_PKTTYPE_GRE = 0x18, + FM10K_PKTTYPE_VXLAN = 0x20, + FM10K_PKTTYPE_NVGRE = 0x28, + FM10K_PKTTYPE_GENEVE = 0x30 +}; +#endif #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006 enum fm10k_rxdesc_xc { @@ -826,6 +873,9 @@ enum fm10k_rxdesc_xc { #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */ #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */ +#if !defined(EXTERNAL_RELEASE) || defined(DPDK_SUPPORT) +#define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */ +#endif #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */ #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */ #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */