diff mbox

[dpdk-dev] net/thunderx: update sq config register field

Message ID 20170711135426.10874-1-jerin.jacob@caviumnetworks.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues

Commit Message

Jerin Jacob July 11, 2017, 1:54 p.m. UTC 
  cq_limit field is added in cn88xx-pass2 and subsequent
versions. Reflect the change in the sq_config structure.
This change is backward compatible as the old pass versions
ignore this field.

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
 drivers/net/thunderx/base/nicvf_hw.c      | 1 +
 drivers/net/thunderx/base/nicvf_hw_defs.h | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

Comments

Ferruh Yigit July 18, 2017, 9:40 a.m. UTC | #1 
On 7/11/2017 2:54 PM, Jerin Jacob wrote:
> cq_limit field is added in cn88xx-pass2 and subsequent
> versions. Reflect the change in the sq_config structure.
> This change is backward compatible as the old pass versions
> ignore this field.
> 
> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>

Applied to dpdk-next-net/master, thanks.
diff mbox

Patch

diff --git a/drivers/net/thunderx/base/nicvf_hw.c b/drivers/net/thunderx/base/nicvf_hw.c
index d10d2c0e0..2634285eb 100644
--- a/drivers/net/thunderx/base/nicvf_hw.c
+++ b/drivers/net/thunderx/base/nicvf_hw.c
@@ -586,6 +586,7 @@  nicvf_qset_sq_config(struct nicvf *nic, uint16_t qidx, struct nicvf_txq *txq)
 	nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE, qidx, txq->phys);
 
 	/* Enable send queue  & set queue size */
+	sq_cfg.cq_limit = 0;
 	sq_cfg.ena = 1;
 	sq_cfg.reset = 0;
 	sq_cfg.ldwb = 0;
diff --git a/drivers/net/thunderx/base/nicvf_hw_defs.h b/drivers/net/thunderx/base/nicvf_hw_defs.h
index b77f4d4a1..0fe673e6d 100644
--- a/drivers/net/thunderx/base/nicvf_hw_defs.h
+++ b/drivers/net/thunderx/base/nicvf_hw_defs.h
@@ -1084,7 +1084,8 @@  struct cq_cfg { union { struct {
 
 struct sq_cfg { union { struct {
 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
-	uint64_t reserved_20_63:44;
+	uint64_t reserved_32_63:32;
+	uint64_t cq_limit:8;
 	uint64_t ena:1;
 	uint64_t reserved_18_18:1;
 	uint64_t reset:1;
@@ -1102,7 +1103,8 @@  struct sq_cfg { union { struct {
 	uint64_t reset:1;
 	uint64_t reserved_18_18:1;
 	uint64_t ena:1;
-	uint64_t reserved_20_63:44;
+	uint64_t cq_limit:8;
+	uint64_t reserved_32_63:32;
 #endif
 	};
 	uint64_t value;