From patchwork Fri Oct 6 15:45:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 29825 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6F5A61B24D; Fri, 6 Oct 2017 17:46:34 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id C932F1B23B for ; Fri, 6 Oct 2017 17:46:31 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from xuemingl@mellanox.com) with ESMTPS (AES256-SHA encrypted); 6 Oct 2017 17:46:28 +0200 Received: from dev-r630-06.mtbc.labs.mlnx (dev-r630-06.mtbc.labs.mlnx [10.12.205.180]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v96FkRPM001997; Fri, 6 Oct 2017 18:46:28 +0300 Received: from dev-r630-06.mtbc.labs.mlnx (localhost [127.0.0.1]) by dev-r630-06.mtbc.labs.mlnx (8.14.7/8.14.7) with ESMTP id v96FkReF161231; Fri, 6 Oct 2017 23:46:27 +0800 Received: (from xuemingl@localhost) by dev-r630-06.mtbc.labs.mlnx (8.14.7/8.14.7/Submit) id v96FkRnR161230; Fri, 6 Oct 2017 23:46:27 +0800 From: Xueming Li To: Nelio Laranjeiro , ferruh.yigit@intel.com Cc: Xueming Li , dev@dpdk.org Date: Fri, 6 Oct 2017 23:45:52 +0800 Message-Id: <20171006154552.161159-6-xuemingl@mellanox.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20171006154552.161159-1-xuemingl@mellanox.com> References: <20171006154552.161159-1-xuemingl@mellanox.com> In-Reply-To: <20170824140341.95471-1-xuemingl@mellanox.com> References: <20170824140341.95471-1-xuemingl@mellanox.com> Subject: [dpdk-dev] [PATCH v5 5/5] net/mlx5: multi-process document update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch update the feature list and NIC guide to be multi-process enabled. Signed-off-by: Xueming Li Acked-by: Nelio Laranjeiro --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index 4a2c3a6..c363639 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -35,6 +35,7 @@ Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y +Multiprocess aware = Y Other kdrv = Y ARMv8 = Y Power8 = Y diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index be0e91c..d24941a 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -92,7 +92,7 @@ Features - Flow director (RTE_FDIR_MODE_PERFECT, RTE_FDIR_MODE_PERFECT_MAC_VLAN and RTE_ETH_FDIR_REJECT). - Flow API. -- Secondary process TX is supported. +- Multiple process. - KVM and VMware ESX SR-IOV modes are supported. - RSS hash result is supported. - Hardware TSO. @@ -106,7 +106,7 @@ Limitations - Inner RSS for VXLAN frames is not supported yet. - Port statistics through software counters only. - Hardware checksum RX offloads for VXLAN inner header are not supported yet. -- Secondary process RX is not supported. +- Forked secondary process not supported. - Flow pattern without any specific vlan will match for vlan packets as well: When VLAN spec is not specified in the pattern, the matching rule will be created with VLAN as a wild card.