From patchwork Mon Mar 12 17:26:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jasvinder Singh X-Patchwork-Id: 36028 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D40F31B3E2; Mon, 12 Mar 2018 18:53:09 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 26F08AAC3 for ; Mon, 12 Mar 2018 18:52:48 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2018 10:27:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,462,1515484800"; d="scan'208";a="182013210" Received: from silpixa00381635.ir.intel.com (HELO silpixa00381635.ger.corp.intel.com) ([10.237.222.149]) by orsmga004.jf.intel.com with ESMTP; 12 Mar 2018 10:27:09 -0700 From: Jasvinder Singh To: dev@dpdk.org Cc: cristian.dumitrescu@intel.com, Kevin Laatz Date: Mon, 12 Mar 2018 17:26:10 +0000 Message-Id: <20180312172615.6621-40-jasvinder.singh@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20180312172615.6621-1-jasvinder.singh@intel.com> References: <20180309182426.135278-2-jasvinder.singh@intel.com> <20180312172615.6621-1-jasvinder.singh@intel.com> Subject: [dpdk-dev] [PATCH v2 39/44] ip_pipeline: add l2fwd example X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch add the configuration file for l2fwd example. It includes commands to build the packet processing stage (pipeline), defining action, add rules to its table, etc. Signed-off-by: Cristian Dumitrescu Signed-off-by: Jasvinder Singh Signed-off-by: Kevin Laatz --- examples/ip_pipeline/examples/l2fwd.cli | 53 +++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 examples/ip_pipeline/examples/l2fwd.cli diff --git a/examples/ip_pipeline/examples/l2fwd.cli b/examples/ip_pipeline/examples/l2fwd.cli new file mode 100644 index 0000000..5b9d529 --- /dev/null +++ b/examples/ip_pipeline/examples/l2fwd.cli @@ -0,0 +1,53 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2010-2018 Intel Corporation + +; The pipeline below implements a simple pass-through connection between the +; input ports to the output ports, as in this diagram: +; ________________ +; LINK0 RXQ0 --->|................|---> LINK1 TXQ0 +; | | +; LINK1 RXQ0 --->|................|---> LINK0 TXQ0 +; | PIPELINE0 | +; LINK2 RXQ0 --->|................|---> LINK3 TXQ0 +; | | +; LINK3 RXQ0 --->|................|---> LINK2 TXQ0 +; |________________| +; + +mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 + +link LINK0 dev 0000:02:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK1 dev 0000:02:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK2 dev 0000:06:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on +link LINK3 dev 0000:06:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on + +table action profile AP0 ipv4 offset 270 fwd + +pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0 + +pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0 + +pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0 +pipeline PIPELINE0 port out bsz 32 link LINK1 txq 0 +pipeline PIPELINE0 port out bsz 32 link LINK2 txq 0 +pipeline PIPELINE0 port out bsz 32 link LINK3 txq 0 + +pipeline PIPELINE0 table match stub action AP0 +pipeline PIPELINE0 table match stub action AP0 +pipeline PIPELINE0 table match stub action AP0 +pipeline PIPELINE0 table match stub action AP0 + +pipeline PIPELINE0 port in 0 table 0 +pipeline PIPELINE0 port in 1 table 1 +pipeline PIPELINE0 port in 2 table 2 +pipeline PIPELINE0 port in 3 table 3 + +thread 1 pipeline PIPELINE0 enable + +pipeline PIPELINE0 table 0 rule add match default action fwd port 1 +pipeline PIPELINE0 table 1 rule add match default action fwd port 0 +pipeline PIPELINE0 table 2 rule add match default action fwd port 3 +pipeline PIPELINE0 table 3 rule add match default action fwd port 2