From patchwork Thu May 3 19:37:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "John Daley (johndale)" X-Patchwork-Id: 39359 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 22C1520BD; Thu, 3 May 2018 21:37:27 +0200 (CEST) Received: from alln-iport-7.cisco.com (alln-iport-7.cisco.com [173.37.142.94]) by dpdk.org (Postfix) with ESMTP id 4C7EBDED for ; Thu, 3 May 2018 21:37:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=@cisco.com; l=3038; q=dns/txt; s=iport; t=1525376245; x=1526585845; h=from:to:cc:subject:date:message-id; bh=GWnnrgZQbBuxIKIVRQ5eTs4kvEBB+AmFwq53eBZsTYk=; b=BmMmigQTfuPx1RjDvl2c47U+Xdih4afijQqIkZh4xtkov5deWzz32v53 lGn0v9D3mWJJh5WlGml2qwbEMxa1iOJxigZ8yURNLN91M5iWyzJy8QPds loSN0YaTjzMoNOazl9h6uORyUk8I2kECj+WTZ0irHJ6yjEIQqUXOFt4EC Q=; X-IronPort-AV: E=Sophos;i="5.49,359,1520899200"; d="scan'208";a="108496729" Received: from alln-core-10.cisco.com ([173.36.13.132]) by alln-iport-7.cisco.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 May 2018 19:37:24 +0000 Received: from cisco.com (savbu-usnic-a.cisco.com [10.193.184.48]) by alln-core-10.cisco.com (8.14.5/8.14.5) with ESMTP id w43JbOmJ020239; Thu, 3 May 2018 19:37:24 GMT Received: by cisco.com (Postfix, from userid 392789) id E22E520F2001; Thu, 3 May 2018 12:37:23 -0700 (PDT) From: John Daley To: ferruh.yigit@intel.com Cc: dev@dpdk.org, Hyong Youb Kim Date: Thu, 3 May 2018 12:37:08 -0700 Message-Id: <20180503193713.20622-1-johndale@cisco.com> X-Mailer: git-send-email 2.16.2 Subject: [dpdk-dev] [PATCH 1/6] net/enic: enable RQ first and then post Rx buffers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hyong Youb Kim Future VIC adapters may require that the driver enable RQ before posting new buffers to the NIC. So split enic_alloc_rx_queue_mbufs() into two functions, one that allocates buffers and fills RQ and the other that posts them (i.e. PIO write to a doorbell). And, call the post function only after enabling RQ. Currently released models are not affected by this change, as they work fine whether the driver posts buffers before or after enabling RQ. Signed-off-by: Hyong Youb Kim Reviewed-by: John Daley Reviewed-by: Aaron Conole --- drivers/net/enic/base/vnic_rq.h | 2 ++ drivers/net/enic/enic_main.c | 27 +++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/net/enic/base/vnic_rq.h b/drivers/net/enic/base/vnic_rq.h index d774bb0db..9619290de 100644 --- a/drivers/net/enic/base/vnic_rq.h +++ b/drivers/net/enic/base/vnic_rq.h @@ -6,6 +6,7 @@ #ifndef _VNIC_RQ_H_ #define _VNIC_RQ_H_ +#include #include "vnic_dev.h" #include "vnic_cq.h" @@ -69,6 +70,7 @@ struct vnic_rq { struct rte_mbuf *pkt_last_seg; unsigned int max_mbufs_per_pkt; uint16_t tot_nb_desc; + bool need_initial_post; }; static inline unsigned int vnic_rq_desc_avail(struct vnic_rq *rq) diff --git a/drivers/net/enic/enic_main.c b/drivers/net/enic/enic_main.c index 2a2269794..e2adadcc9 100644 --- a/drivers/net/enic/enic_main.c +++ b/drivers/net/enic/enic_main.c @@ -315,6 +315,24 @@ enic_alloc_rx_queue_mbufs(struct enic *enic, struct vnic_rq *rq) rq_buf_len); rq->mbuf_ring[i] = mb; } + /* + * Do not post the buffers to the NIC until we enable the RQ via + * enic_start_rq(). + */ + rq->need_initial_post = true; + return 0; +} + +/* + * Post the Rx buffers for the first time. enic_alloc_rx_queue_mbufs() has + * allocated the buffers and filled the RQ descriptor ring. Just need to push + * the post index to the NIC. + */ +static void +enic_initial_post_rx(struct enic *enic, struct vnic_rq *rq) +{ + if (!rq->in_use || !rq->need_initial_post) + return; /* make sure all prior writes are complete before doing the PIO write */ rte_rmb(); @@ -329,9 +347,7 @@ enic_alloc_rx_queue_mbufs(struct enic *enic, struct vnic_rq *rq) iowrite32(rq->posted_index, &rq->ctrl->posted_index); iowrite32(0, &rq->ctrl->fetch_index); rte_rmb(); - - return 0; - + rq->need_initial_post = false; } static void * @@ -619,10 +635,13 @@ void enic_start_rq(struct enic *enic, uint16_t queue_idx) rq_data = &enic->rq[rq_sop->data_queue_idx]; struct rte_eth_dev *eth_dev = enic->rte_dev; - if (rq_data->in_use) + if (rq_data->in_use) { vnic_rq_enable(rq_data); + enic_initial_post_rx(enic, rq_data); + } rte_mb(); vnic_rq_enable(rq_sop); + enic_initial_post_rx(enic, rq_sop); eth_dev->data->rx_queue_state[queue_idx] = RTE_ETH_QUEUE_STATE_STARTED; }