[dpdk-dev,v2] net/mlx5: fix memory region cache init

Message ID 20180526132735.21751-1-xuemingl@mellanox.com (mailing list archive)
State Accepted, archived
Delegated to: Shahaf Shuler
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail apply patch file failure

Commit Message

Xueming Li May 26, 2018, 1:27 p.m. UTC
  This patch moved MR cache init from device configuration function to
probe function to make sure init only once.

Fixes: 974f1e7ef146 ("net/mlx5: add new memory region support")
Cc: yskoh@mellanox.com

Signed-off-by: Xueming Li <xuemingl@mellanox.com>
---
 drivers/net/mlx5/mlx5.c        | 13 +++++++++++++
 drivers/net/mlx5/mlx5_ethdev.c | 11 -----------
 drivers/net/mlx5/mlx5_mr.c     |  1 +
 3 files changed, 14 insertions(+), 11 deletions(-)
  

Comments

Yongseok Koh May 26, 2018, 5:08 p.m. UTC | #1
> On May 26, 2018, at 6:28 AM, Xueming Li <xuemingl@mellanox.com> wrote:
> 
> This patch moved MR cache init from device configuration function to
> probe function to make sure init only once.
> 
> Fixes: 974f1e7ef146 ("net/mlx5: add new memory region support")
> Cc: yskoh@mellanox.com
> 
> Signed-off-by: Xueming Li <xuemingl@mellanox.com>
> ---
Acked-by: Yongseok Koh <yskoh@mellanox.com>

Thanks
  
Shahaf Shuler May 27, 2018, 5:05 a.m. UTC | #2
Saturday, May 26, 2018 8:08 PM, Yongseok Koh:
> Subject: Re: [PATCH v2] net/mlx5: fix memory region cache init
> 
> 
> > On May 26, 2018, at 6:28 AM, Xueming Li <xuemingl@mellanox.com>
> wrote:
> >
> > This patch moved MR cache init from device configuration function to
> > probe function to make sure init only once.
> >
> > Fixes: 974f1e7ef146 ("net/mlx5: add new memory region support")
> > Cc: yskoh@mellanox.com
> >
> > Signed-off-by: Xueming Li <xuemingl@mellanox.com>
> > ---
> Acked-by: Yongseok Koh <yskoh@mellanox.com>

Applied to next-net-mlx, thanks. 

> 
> Thanks
  
Shahaf Shuler May 27, 2018, 5:08 a.m. UTC | #3
Ferruh,

Sunday, May 27, 2018 8:05 AM, Shahaf Shuler:
> Subject: Re: [dpdk-dev] [PATCH v2] net/mlx5: fix memory region cache init
> 
> Saturday, May 26, 2018 8:08 PM, Yongseok Koh:
> > Subject: Re: [PATCH v2] net/mlx5: fix memory region cache init
> >
> >
> > > On May 26, 2018, at 6:28 AM, Xueming Li <xuemingl@mellanox.com>
> > wrote:
> > >
> > > This patch moved MR cache init from device configuration function to
> > > probe function to make sure init only once.
> > >
> > > Fixes: 974f1e7ef146 ("net/mlx5: add new memory region support")
> > > Cc: yskoh@mellanox.com
> > >
> > > Signed-off-by: Xueming Li <xuemingl@mellanox.com>
> > > ---
> > Acked-by: Yongseok Koh <yskoh@mellanox.com>
> 
> Applied to next-net-mlx, thanks.

This is yet another critical fix for a bug caught recently. 
This patch is to prevent deadlock when restarting the port.  

Hope you will be able to pull this one in. 

> 
> >
> > Thanks
  

Patch

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index dae847493..3ef02e2d2 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1193,6 +1193,19 @@  mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 			goto port_error;
 		}
 		priv->config.max_verbs_prio = verb_priorities;
+		/*
+		 * Once the device is added to the list of memory event
+		 * callback, its global MR cache table cannot be expanded
+		 * on the fly because of deadlock. If it overflows, lookup
+		 * should be done by searching MR list linearly, which is slow.
+		 */
+		err = mlx5_mr_btree_init(&priv->mr.cache,
+					 MLX5_MR_BTREE_CACHE_N * 2,
+					 eth_dev->device->numa_node);
+		if (err) {
+			err = rte_errno;
+			goto port_error;
+		}
 		/* Add device to memory callback list. */
 		rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 		LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index f6cebae41..90488af33 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -392,17 +392,6 @@  mlx5_dev_configure(struct rte_eth_dev *dev)
 		if (++j == rxqs_n)
 			j = 0;
 	}
-	/*
-	 * Once the device is added to the list of memory event callback, its
-	 * global MR cache table cannot be expanded on the fly because of
-	 * deadlock. If it overflows, lookup should be done by searching MR list
-	 * linearly, which is slow.
-	 */
-	if (mlx5_mr_btree_init(&priv->mr.cache, MLX5_MR_BTREE_CACHE_N * 2,
-			       dev->device->numa_node)) {
-		/* rte_errno is already set. */
-		return -rte_errno;
-	}
 	return 0;
 }
 
diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c
index abb1f5179..08105a443 100644
--- a/drivers/net/mlx5/mlx5_mr.c
+++ b/drivers/net/mlx5/mlx5_mr.c
@@ -191,6 +191,7 @@  mlx5_mr_btree_init(struct mlx5_mr_btree *bt, int n, int socket)
 		rte_errno = EINVAL;
 		return -rte_errno;
 	}
+	assert(!bt->table && !bt->size);
 	memset(bt, 0, sizeof(*bt));
 	bt->table = rte_calloc_socket("B-tree table",
 				      n, sizeof(struct mlx5_mr_cache),