diff mbox series

[v3,1/3] common/qat: add QAT RAM bank definitions

Message ID 20190920200628.6444-2-adamx.dybkowski@intel.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers show
Series compress/qat: add stateful decompression | expand

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-dpdk_compile_ovs success Compile Testing PASS
ci/iol-dpdk_compile_spdk success Compile Testing PASS
ci/iol-dpdk_compile success Compile Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS

Commit Message

Dybkowski, AdamX Sept. 20, 2019, 8:06 p.m. UTC
This patch adds QAT RAM bank definitions and related macros.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 73 ++++++++++++++++++++
 1 file changed, 73 insertions(+)

Comments

Fiona Trahe Sept. 24, 2019, 11:16 a.m. UTC | #1
> -----Original Message-----
> From: Dybkowski, AdamX
> Sent: Friday, September 20, 2019 9:06 PM
> To: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; Trybula, ArturX
> <arturx.trybula@intel.com>; akhil.goyal@nxp.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH v3 1/3] common/qat: add QAT RAM bank definitions
> 
> This patch adds QAT RAM bank definitions and related macros.
> 
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
diff mbox series

Patch

diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
index 813817720..c89a2c2fd 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -479,4 +479,77 @@  struct icp_qat_fw_comp_resp {
 	/**< Common response params (checksums and byte counts) */
 };
 
+/* RAM Bank definitions */
+#define QAT_FW_COMP_BANK_FLAG_MASK 0x1
+
+#define QAT_FW_COMP_BANK_I_BITPOS 8
+#define QAT_FW_COMP_BANK_H_BITPOS 7
+#define QAT_FW_COMP_BANK_G_BITPOS 6
+#define QAT_FW_COMP_BANK_F_BITPOS 5
+#define QAT_FW_COMP_BANK_E_BITPOS 4
+#define QAT_FW_COMP_BANK_D_BITPOS 3
+#define QAT_FW_COMP_BANK_C_BITPOS 2
+#define QAT_FW_COMP_BANK_B_BITPOS 1
+#define QAT_FW_COMP_BANK_A_BITPOS 0
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_comp
+ *      Definition of the ram bank enabled values
+ * @description
+ *      Enumeration used to define whether a ram bank is enabled or not
+ *
+ *****************************************************************************/
+enum icp_qat_fw_comp_bank_enabled {
+	ICP_QAT_FW_COMP_BANK_DISABLED = 0, /*!< BANK DISABLED */
+	ICP_QAT_FW_COMP_BANK_ENABLED = 1,  /*!< BANK ENABLED */
+	ICP_QAT_FW_COMP_BANK_DELIMITER = 2 /**< Delimiter type */
+};
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_comp
+ *
+ * @description
+ *      Build the ram bank flags in the compression content descriptor
+ *      which specify which banks are used to save history
+ *
+ * @param bank_i_enable
+ * @param bank_h_enable
+ * @param bank_g_enable
+ * @param bank_f_enable
+ * @param bank_e_enable
+ * @param bank_d_enable
+ * @param bank_c_enable
+ * @param bank_b_enable
+ * @param bank_a_enable
+ *****************************************************************************/
+#define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable,                         \
+					bank_h_enable,                         \
+					bank_g_enable,                         \
+					bank_f_enable,                         \
+					bank_e_enable,                         \
+					bank_d_enable,                         \
+					bank_c_enable,                         \
+					bank_b_enable,                         \
+					bank_a_enable)                         \
+	((((bank_i_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                         \
+		<< QAT_FW_COMP_BANK_I_BITPOS) |                                \
+	(((bank_h_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_H_BITPOS) |                                \
+	(((bank_g_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_G_BITPOS) |                                \
+	(((bank_f_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_F_BITPOS) |                                \
+	(((bank_e_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_E_BITPOS) |                                \
+	(((bank_d_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_D_BITPOS) |                                \
+	(((bank_c_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_C_BITPOS) |                                \
+	(((bank_b_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_B_BITPOS) |                                \
+	(((bank_a_enable)&QAT_FW_COMP_BANK_FLAG_MASK)                          \
+		<< QAT_FW_COMP_BANK_A_BITPOS))
+
 #endif