From patchwork Thu Dec 5 12:38:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 63591 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5616DA04F2; Thu, 5 Dec 2019 13:37:12 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 483721BFBF; Thu, 5 Dec 2019 13:36:08 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 1C6FD1BF9B for ; Thu, 5 Dec 2019 13:35:54 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Dec 2019 04:35:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,281,1571727600"; d="scan'208";a="209122760" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga008.fm.intel.com with ESMTP; 05 Dec 2019 04:35:53 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Kiran Patil , Paul M Stillwell Jr Date: Thu, 5 Dec 2019 20:38:44 +0800 Message-Id: <20191205123847.39579-10-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191205123847.39579-1-qi.z.zhang@intel.com> References: <20191205123847.39579-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 09/12] net/ice/base: change fdir desc preparation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Change internal implemenatation of how FD filter programming desc is prepared. This is to minimize the amount of code needed to prep the FD filter programming desc (avoid memcpy, etc...) and just use predefined shifts and mask. This type of change are needed to expedite FD setup during data path (ADQ uses this codepath during initial flow setup) and it will also be useful when adding side-band flow-director filter. Signed-off-by: Kiran Patil Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.c | 92 ++++++++++++++++++++++++----------------- 1 file changed, 55 insertions(+), 37 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 37b388169..87fa0afba 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -352,35 +352,6 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = { #define ICE_FDIR_NUM_PKT ARRAY_SIZE(ice_fdir_pkt) -/* Flow Direcotr (FD) filter program descriptor Context */ -static const struct ice_ctx_ele ice_fd_fltr_desc_ctx_info[] = { - /* Field Width LSB */ - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, qindex, 11, 0), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_q, 1, 11), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_report, 2, 12), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_space, 2, 14), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_index, 13, 16), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_ena, 2, 29), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, evict_ena, 1, 31), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq, 3, 32), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq_prio, 3, 35), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, dpu_recipe, 2, 38), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, drop, 1, 40), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_prio, 3, 41), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_mdid, 4, 44), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_val, 16, 48), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, dtype, 4, 64), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, pcmd, 1, 68), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof_prio, 3, 69), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof, 6, 72), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_vsi, 10, 78), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, swap, 1, 88), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_prio, 3, 89), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_mdid, 4, 92), - ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid, 32, 96), - { 0 } -}; - /** * ice_set_dflt_val_fd_desc * @fd_fltr_ctx: pointer to fd filter descriptor @@ -455,19 +426,66 @@ ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input, /** * ice_set_fd_desc_val - * @fd_fltr_ctx: pointer to fd filter descriptor context + * @ctx: pointer to fd filter descriptor context * @fdir_desc: populated with fd filter descriptor values */ void -ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx, +ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx, struct ice_fltr_desc *fdir_desc) { - u64 ctx_buf[2] = { 0 }; - - ice_set_ctx((u8 *)fd_fltr_ctx, (u8 *)ctx_buf, - ice_fd_fltr_desc_ctx_info); - fdir_desc->qidx_compq_space_stat = CPU_TO_LE64(ctx_buf[0]); - fdir_desc->dtype_cmd_vsi_fdid = CPU_TO_LE64(ctx_buf[1]); + u64 qword; + + /* prep QW0 of FD filter programming desc */ + qword = ((u64)ctx->qindex << ICE_FXD_FLTR_QW0_QINDEX_S) & + ICE_FXD_FLTR_QW0_QINDEX_M; + qword |= ((u64)ctx->comp_q << ICE_FXD_FLTR_QW0_COMP_Q_S) & + ICE_FXD_FLTR_QW0_COMP_Q_M; + qword |= ((u64)ctx->comp_report << ICE_FXD_FLTR_QW0_COMP_REPORT_S) & + ICE_FXD_FLTR_QW0_COMP_REPORT_M; + qword |= ((u64)ctx->fd_space << ICE_FXD_FLTR_QW0_FD_SPACE_S) & + ICE_FXD_FLTR_QW0_FD_SPACE_M; + qword |= ((u64)ctx->cnt_index << ICE_FXD_FLTR_QW0_STAT_CNT_S) & + ICE_FXD_FLTR_QW0_STAT_CNT_M; + qword |= ((u64)ctx->cnt_ena << ICE_FXD_FLTR_QW0_STAT_ENA_S) & + ICE_FXD_FLTR_QW0_STAT_ENA_M; + qword |= ((u64)ctx->evict_ena << ICE_FXD_FLTR_QW0_EVICT_ENA_S) & + ICE_FXD_FLTR_QW0_EVICT_ENA_M; + qword |= ((u64)ctx->toq << ICE_FXD_FLTR_QW0_TO_Q_S) & + ICE_FXD_FLTR_QW0_TO_Q_M; + qword |= ((u64)ctx->toq_prio << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) & + ICE_FXD_FLTR_QW0_TO_Q_PRI_M; + qword |= ((u64)ctx->dpu_recipe << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) & + ICE_FXD_FLTR_QW0_DPU_RECIPE_M; + qword |= ((u64)ctx->drop << ICE_FXD_FLTR_QW0_DROP_S) & + ICE_FXD_FLTR_QW0_DROP_M; + qword |= ((u64)ctx->flex_prio << ICE_FXD_FLTR_QW0_FLEX_PRI_S) & + ICE_FXD_FLTR_QW0_FLEX_PRI_M; + qword |= ((u64)ctx->flex_mdid << ICE_FXD_FLTR_QW0_FLEX_MDID_S) & + ICE_FXD_FLTR_QW0_FLEX_MDID_M; + qword |= ((u64)ctx->flex_val << ICE_FXD_FLTR_QW0_FLEX_VAL_S) & + ICE_FXD_FLTR_QW0_FLEX_VAL_M; + fdir_desc->qidx_compq_space_stat = CPU_TO_LE64(qword); + + /* prep QW1 of FD filter programming desc */ + qword = ((u64)ctx->dtype << ICE_FXD_FLTR_QW1_DTYPE_S) & + ICE_FXD_FLTR_QW1_DTYPE_M; + qword |= ((u64)ctx->pcmd << ICE_FXD_FLTR_QW1_PCMD_S) & + ICE_FXD_FLTR_QW1_PCMD_M; + qword |= ((u64)ctx->desc_prof_prio << ICE_FXD_FLTR_QW1_PROF_PRI_S) & + ICE_FXD_FLTR_QW1_PROF_PRI_M; + qword |= ((u64)ctx->desc_prof << ICE_FXD_FLTR_QW1_PROF_S) & + ICE_FXD_FLTR_QW1_PROF_M; + qword |= ((u64)ctx->fd_vsi << ICE_FXD_FLTR_QW1_FD_VSI_S) & + ICE_FXD_FLTR_QW1_FD_VSI_M; + qword |= ((u64)ctx->swap << ICE_FXD_FLTR_QW1_SWAP_S) & + ICE_FXD_FLTR_QW1_SWAP_M; + qword |= ((u64)ctx->fdid_prio << ICE_FXD_FLTR_QW1_FDID_PRI_S) & + ICE_FXD_FLTR_QW1_FDID_PRI_M; + qword |= ((u64)ctx->fdid_mdid << ICE_FXD_FLTR_QW1_FDID_MDID_S) & + ICE_FXD_FLTR_QW1_FDID_MDID_M; + qword |= ((u64)ctx->fdid << ICE_FXD_FLTR_QW1_FDID_S) & + ICE_FXD_FLTR_QW1_FDID_M; + fdir_desc->dtype_cmd_vsi_fdid = CPU_TO_LE64(qword); } /**