[v2,07/17] net/enic: add checks for max SIMD bitwidth

Message ID 20200827161304.32300-8-ciara.power@intel.com (mailing list archive)
State Superseded, archived
Delegated to: David Marchand
Series add max SIMD bitwidth to EAL |


Context Check Description
ci/checkpatch success coding style OK

Commit Message

Power, Ciara Aug. 27, 2020, 4:12 p.m. UTC
  When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled

Cc: John Daley <johndale@cisco.com>
Cc: Hyong Youb Kim <hyonkim@cisco.com>

Acked-by: Hyong Youb Kim <hyonkim@cisco.com>
Signed-off-by: Ciara Power <ciara.power@intel.com>
 drivers/net/enic/enic_rxtx_vec_avx2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)


diff --git a/drivers/net/enic/enic_rxtx_vec_avx2.c b/drivers/net/enic/enic_rxtx_vec_avx2.c
index 676b9f5fdb..5db43bdbb8 100644
--- a/drivers/net/enic/enic_rxtx_vec_avx2.c
+++ b/drivers/net/enic/enic_rxtx_vec_avx2.c
@@ -821,7 +821,8 @@  enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev)
 	fconf = &eth_dev->data->dev_conf.fdir_conf;
 	if (fconf->mode != RTE_FDIR_MODE_NONE)
 		return false;
-	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) {
+	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) &&
+			rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) {
 		ENICPMD_LOG(DEBUG, " use the non-scatter avx2 Rx handler");
 		eth_dev->rx_pkt_burst = &enic_noscatter_vec_recv_pkts;
 		enic->use_noscatter_vec_rx_handler = 1;